Precision at Scale: System Design from Tiny Biosensors to Giant Arrays Citation Gal-Katziri, Matan (2021) Precision at Scale: System Design from Tiny Biosensors to Giant Arrays. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/t3cz-c785. https://resolver.caltech.edu/CaltechTHESIS:08172020-115024354 Abstract In order to change the world, technological advancements must be made affordable and available for the general public to use. In other words, we must be able to scale our inventions effectively. Silicon integrated circuits are crucial components in scaling electronic systems because they are mass producible and offer a phenomenal cost-to-complexity ratio. This thesis summarizes the author’s work on highly scalable sensor and array systems. It presents three high precision systems, that demonstrate how the use of highly functional radio-frequency integrated circuits enables the realization of previously unfeasible architectures. Item Type: Thesis (Dissertation (Ph.D.)) Subject Keywords: Biosensors, bridge circuits, CMOS integrated circuits, inductive transducers, magnetic sensors flexible electronics, phased array, integrated circuits, calibration, wireless power transfer. Degree Grantor: California Institute of Technology Division: Engineering and Applied Science Major Option: Electrical Engineering Thesis Availability: Public (worldwide access) Research Advisor(s): Hajimiri, Ali Thesis Committee: Emami, Azita (chair) Weinreb, Sander Marandi, Alireza Hajimiri, Ali Defense Date: 24 July 2020 Record Number: CaltechTHESIS:08172020-115024354 Persistent URL: https://resolver.caltech.edu/CaltechTHESIS:08172020-115024354 DOI: 10.7907/t3cz-c785 Related URLs: URL URL Type Description https://doi.org/10.1109/JSSC.2019.2907196 DOI Article adapted for Ch. 1 https://doi.org/10.1038/s41928-019-0247-9 DOI Article adapted for Ch. 3 https://doi.org/10.1109/ESSCIRC.2018.8494313 DOI Article adapted for Ch. 1 https://doi.org/10.2514/6.2018-2202 DOI Article adapted for Ch. 3 https://doi.org/10.1109/PVSC.2018.8547403 DOI Article adapted for Ch. 3 https://doi.org/10.1109/ASSCC.2018.8579340 DOI Article adapted for Ch. 3 ORCID: Author ORCID Gal-Katziri, Matan 0000-0001-9100-1188 Default Usage Policy: No commercial reproduction, distribution, display or performance rights in this work are provided. ID Code: 13857 Collection: CaltechTHESIS Deposited By: Matan Gal Deposited On: 11 Sep 2020 15:38 Last Modified: 12 Jun 2025 00:06 Thesis Files Preview PDF - Final Version See Usage Policy. 33MB Repository Staff Only: item control page

Precision at Scale: System Design from Tiny Biosensors to Giant Arrays Thesis by Matan Gal-Katziri In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy CALIFORNIA INSTITUTE OF TECHNOLOGY Pasadena, California 2020 Defended July 24, 2020 ii © 2020 Matan Gal-Katziri ORCID: 0000-0001-9100-1188 All rights reserved iii To Kim, my love, to our beloved children, and to our loving extended family. iv ACKNOWLEDGEMENTS There is a popular saying that it takes about 10,000 hours of deliberate practice to master a field. The average Caltech graduate student who works 60-80 hours a week throughout the year and graduates in an average of 5.6 years, completes about twice as much hours of training. Besides the impressive result of graduating as a master expert, undertaking such an endeavour is nearly impossible without a supporting circle of family, management, colleagues and friends who deserve special thanks. First and foremost I would like to thank my loving wife Kim. In truth, this thesis would probably not have been written if she hadn’t encouraged me to apply to Caltech’s graduate program. She stood by my side through the transition to a foreign country and through exams, deadlines, and sleepless tapout nights, while making sure that our family and house remain functioning. She is an equal partner to this achievement; I couldn’t have done this without her. Our beloved sons Ivri and Uri also deserve my thanks for being a part of this journey. I hope that one day they will remember with a smile the time that they spent with their father in lab, probably more time than the average undergraduate student does. I am grateful to my advisor, Prof. Ali Hajimiri for the opportunity to work in his research group. It is not trivial to admit an older student with a family, who might turn out to be less productive due to additional commitments. Ali is, of course, an expert in his field, but he holds several other qualities that are less commonly found in academic advisors. It is his saying that in his lab he trains leaders. Indeed, from him I learned that it is not always enough to be technically capable of executing a task: it is the purpose behind an idea, the justification, and foresight of potential expansions that matter. From him I learned that by doing so, I can harness people and resources to achieve meaningful goals. While other electrical engineering groups research contemporary problems, Ali is always looking into the future, and this made the experience of working for him unique. His view and advice on personal and professional matters were always insightful, and have taught me an important lesson in decision-making. I am proud to have him as my mentor. I would also like to thank my thesis committee, Prof. Azita Emami, Sander (Sandy) Weinreb and Alireza Marandi for taking the time and patience to participate in my candidacy and defense presentations. The latter was scheduled amidst the COVID19 pandemic and I greatly appreciate their willingness to attend despite the many v disturbances to their research, family, and life routines. I was fortunate to be a part of Caltech’s Space Solar-Power Program, and to see the innards of a truly ambitious project to send huge power-transmitter satellites into space. I would like to thank all the participating groups and our collaborators for the insightful interaction. I had the pleasure of working closely with Drs. Florian Bohn, Behrooz Abiri, and Amir Safaripour, as well as Austin Fikes and Mohith Manohara. I wish to thank them for the fruitful technical discussions, help, and guidance which were invaluable to completing my Ph.D. work. I also wish to thank my colleagues from our lab who were a significant part of my social and academic life here: Prof. Constantine Sideris, Dr. Alex Pai and Dr. Brian Hong, Aroutin Khachaturian, Reza Fatemi, Parham Khial, and Elliott Williams. Some of the funniest and most fun moments happened with them in and out of the lab, in between our work assignments. I had the pleasure of collaborating with Craig Ives and Armina Khakpour and I would like to wish them the best of luck in their future work. I want to thank all the other lab member in the past and present that I had the honor to meet and work with: Dr. Kaushik Dasgupta, Dr. Reza Hashemi, Dr. Fatemeh Akbar (Noyan), Oren Mizrahi, Samir Nooshabadi, Ailec Wu, Alex White, Garret Sullivan and Stephan Turkowski. Dave Hodge deserves special thanks for keeping our equipment and lab running in an orderly manner despite the students elaborate attempts to destroy them. My work here wouldn’t have been possible without a broader circle of social support. Our Israeli scholars and faculty friends helped us to feel a little bit closer to home. We also formed friendships with several of our children’s families and I would like to thank them all. I would also like to dedicate special thanks to the Children’s Center at Caltech which was a pillar of stability and security through these years. If not for them, I probably wouldn’t have been able to complete my academic duties during the COVID-19 pandemic. Last, but not least I would like to thank our extended family who were a part of this journey. To our parents Ishay and Ayala Katziri and Soli Banaji, and my grandmother Tzvia, who supported us form near and afar. To my late biological father Yaakov Gal who never had the opportunity to see me earn my Ph.D., and to Kim’s mother Marian Eichorn. To our loving brothers and sisters Omer, Alona, Einav, Yael, Lilach and their families. To our family in Pasadena Amy, Dave, Jeff and Allie, and to our cousins from LA Hedy, Jerry, Marge, Richard and Lois, who did everything they could to make us feel at home here in the US. vi ABSTRACT In order to change the world, technological advancements must be made affordable and available for the general public to use. In other words, we must be able to scale our inventions effectively. Silicon integrated circuits are crucial components in scaling electronic systems because they are mass producible and offer a phenomenal cost-to-complexity ratio. This thesis summarizes the author’s work on highly scalable sensor and array systems. It presents three high precision systems, that demonstrate how the use of highly functional radio-frequency integrated circuits enables the realization of previously unfeasible architectures. vii PUBLISHED CONTENT AND CONTRIBUTIONS [1] B. Abiri et al., “A lightweight space-based solar power satellite,” Proceedings of IEEE, In Review, 2020. M.G. was a part of the RF electronics team that developed the RFIC and flexible tile structure. [2] M. Gal-Katziri, A. C. Fikes, F. Bohn, B. Abiri, M. Hashemi, and A. Hajimiri, “Scalable, deployable, flexible phased array sheets,” in 2020 IEEE MTT-S International Microwave Symposium (IMS), 2020. M.G. designed parts of the RFIC, was a partner in the system integration, assembled the flexible array, and carried its measurements. [3] A. Hajimiri et al., “Dynamic focusing of large arrays for wireless power transfer and beyond,” IEEE Journal of Solid-State Circuits, In Review, 2020. M.G. designed parts of the RFIC, worked on the programming interface between the unit cells to a central controller, and wrote an FPGA hardware interface from the main controller to the array sub-units. [4] M. Gal-Katziri and A. Hajimiri, “Analysis and design of coupled inductive bridges for magnetic sensing applications,” IEEE Journal of Solid-State Circuits, vol. 54, no. 7, pp. 1883–1894, 2019. doi: https://doi.org/10. 1109/JSSC.2019.2907196. M.G. developed the generalized concept of energy storage shift, carried analysis, designed and measured a magnetic bridge sensor IC. [5] M. R. M. Hashemi et al., “A flexible phased array system with low areal mass density,” Nature Electronics, vol. 2, no. 5, pp. 195–205, May 2019, issn: 2520-1131. [Online]. Available: https://doi.org/10.1038/s41928019-0247-9. M.G. designed parts of the RFIC and was a partner in the tile design and integration. [6] M. Gal-Katziri and A. Hajimiri, “A coupled inductive bridge for magnetic sensing applications,” in ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), Sep. 2018, pp. 342–345. doi: https : //doi.org/10.1109/ESSCIRC.2018.8494313. M.G. developed the sensor concept, designed the chip, carried out measurements, and presented the material. [7] E. Gdoutos et al., “A lightweight tile structure integrating photovoltaic conversion and rf power transfer for space solar power applications,” in 2018 AIAA Spacecraft Structures Conference. 2018. [Online]. Available: https://arc.aiaa.org/doi/abs/10.2514/6.2018-2202. M.G. was a part of the RF electronics team that developed the RFIC and flexible tile structure. viii [8] M. D. Kelzenberg et al., “Ultralight energy converter tile for the space solar power initiative,” in 2018 IEEE 7th World Conference on Photovoltaic Energy Conversion (WCPEC), 2018, pp. 3357–3359. doi: https://doi. org/10.1109/PVSC.2018.8547403. M.G. was a part of the RF electronics team that developed the RFIC and flexible tile structure. [9] M. Gal-Katziri and A. Hajimiri, “A sub-picosecond hybrid DLL for largescale phased array synchronization,” in 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2018, pp. 231–234. doi: https://doi.org/10. 1109/ASSCC.2018.8579340. M.G. developed the hybrid loop concept, and fabricated and measured the DLL IC. ix TABLE OF CONTENTS Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi Published Content and Contributions . . . . . . . . . . . . . . . . . . . . . . vii Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii List of Illustrations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviii Chapter I: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Chapter II: Analysis and Design of Magnetic Energy-Deviation Sensors . . . 4 2.1 Magnetic Susceptibility Sensors . . . . . . . . . . . . . . . . . . . . 5 2.2 A Survey of Integrated Magnetic Biosensors . . . . . . . . . . . . . 10 2.3 Coupled Inductive Bridge Sensors . . . . . . . . . . . . . . . . . . . 13 2.4 A Coupled Inductive Bridge - Proof-of-Concept Design . . . . . . . 19 2.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Chapter III: Caltech’s Space Solar Power Project . . . . . . . . . . . . . . . . 35 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3 System Level Design . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.4 RFIC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.5 Tile-Level Integration and SSPP Demo . . . . . . . . . . . . . . . . 87 3.6 System-scale Integration . . . . . . . . . . . . . . . . . . . . . . . . 108 Chapter IV: Synchronizing RF Phased Arrays with Light . . . . . . . . . . . 118 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.2 Theoretical Background . . . . . . . . . . . . . . . . . . . . . . . . 119 4.3 Chip Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 x LIST OF ILLUSTRATIONS Number Page 2.1 Arbitrary current density in volume 𝑉0 (a) with, and (b) without a magnetic particle 𝑉𝑝 in the volume. . . . . . . . . . . . . . . . . . . 5 2.2 Magnetic bead with volume 𝑉𝑝 and susceptibility 𝜒 in a space 𝑉0 with an unperturbed magnetic energy density of 𝑢 𝐵0 = 𝐵02 /2𝜇0 . . . . 8 2.3 Planar inductor segmentation as one-dimensional current-loops. . . . 9 2.4 An oscillator circuit (a) with and (b) without a magnetic perturbation in the inductor core. . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 An example of a magnetic perturbation travelling in the vicinity of a transformer-based inductance-shift sensor. . . . . . . . . . . . . . . . 12 2.6 A coupled inductive bridge. (a) Circuit schematics. Inductors with the same color share a core. (b) Physical implementation with a magnetic perturbation near one of the cores (not drawn to scale). . . . 14 2.7 Schematic circuits of the sensor’s (a) input impedance test circuit and (b) output impedance test circuit. . . . . . . . . . . . . . . . . . . . 16 2.8 Schematic circuits of the sensor’s (a) excitation noise and (b) single inductor equivalent thermal noise. . . . . . . . . . . . . . . . . . . . 17 2.9 A high frequency (a) coupled inductor model and (b) exemplary 2-turn layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.10 A high frequency (a) coupled bridge model and (b) equivalent circuit. 19 2.11 Top: complex frequency response of two types of magnetic bead [9]. Bottom: change in magnitude of 𝜒 vs. frequency [15] for three bead types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.12 Coupled bridge design parameters as a function of the inner core diameter and the number of the single-inductor turns. (a) maximum transducer gain, (b) self and mutual inductance, (c) gain ratio, (d) SRF. 21 2.13 Comparison between the calculated and simulated transducer gain as a function of location above the sensor, (left) on 𝑥𝑧-plane, (right) on 𝑦𝑧-plane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.14 Bead location for the calculation of maximum and minimum gain parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 xi 2.15 2.16 2.17 2.18 2.19 2.20 2.21 2.22 2.23 2.24 2.25 2.26 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Simulated magnetic field intensity with core inductors shorted in series. (a) On 𝑥𝑧-plane, (b) on 𝑦𝑧-plane, with (c) recorded values in 𝑑𝐵( 𝐴 · 𝑚 −1 ) (to increase contrast). . . . . . . . . . . . . . . . . . . . Simplified schematics of the fabricated IC. . . . . . . . . . . . . . . General structure of offset cancellation scheme. . . . . . . . . . . . . Attainable offset cancellation as a function of amplitude and phase control number of DAC bits. . . . . . . . . . . . . . . . . . . . . . . Top level view: (a) simplified measurement system schematics and (b) the chip die photo. . . . . . . . . . . . . . . . . . . . . . . . . . Measurement vs. simulation of (a) input power saturation, and of (b) input matching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparison between the simulated and measured OC path gain to the simulated receiver gain. . . . . . . . . . . . . . . . . . . . . . . Probe locations for gain profile characterization. . . . . . . . . . . . Gain profile degradation vs. height on 𝑦𝑧-plane (right) and 𝑥𝑧-plane (middle) compared to simulation prediction (left). . . . . . . . . . . Measurement system, including OC circuitry. . . . . . . . . . . . . . Exemplary system response to different amounts of 4.5𝜇m iron-oxide beads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sensor cell response for 4.5𝜇m beads at various locations on the core surface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Glaser’s original patent drawing of a solar power satellite. . . . . . . Cost of expeditionary power. Both JP8 cost and the JP8 cost of transport to destination affect total cost in operation [40]. . . . . . . . 𝑁 𝑆𝑉 and 𝑁 𝐿 are linearly dependent on 𝑃𝑔 . The slopes of the curves depend on the specifics of the space vehicle [41]. . . . . . . . . . . . Space segment contribution to LCOE vs. spacecraft specific power. . Space segment contribution to LCOE vs. reduction in the cost of build and launch of an SSP spacecraft. . . . . . . . . . . . . . . . . . Achievable efficiency for given PER, quality factor, and number of output matching stages [55]. . . . . . . . . . . . . . . . . . . . . . . Power amplifier efficiency versus frequency as a combination of passive and active component efficiencies (Fig. courtesy of Dr. F. Bohn). SSP array size and its far-field spot size versus frequency of operation (Fig. courtesy of Dr. F. Bohn). . . . . . . . . . . . . . . . . . . . . . FCC’s graph of RF attenuation through the atmosphere [57][58] . . . 24 26 26 27 28 29 29 30 31 32 33 33 36 38 42 44 45 48 48 49 50 xii 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.23 3.24 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 Change in (a) number of antennas per unit area and (b) power supply to be radiated by each antenna vs. frequency of operation. . . . . . . 51 Conceptual SSP array: (a) Array, spacecraft, panel and tile levels and (b) concept of operation of an SSP sheet PV-RF power conversion system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SSP spacecraft packaging: (a) Deployed, (b) collapsed plain, (c) folded inwards, (d) collapsed sideways and rolled, and (e) packed [59]. 53 Comparison of (a) a single-sided RF/PV vs. (b) a dual-sided RF/PV SSP spacecraft coverage [41]. . . . . . . . . . . . . . . . . . . . . . 54 A photo of an SSP tile prototype. . . . . . . . . . . . . . . . . . . . 56 IC temperature in space due to heat dissipation on (a) a square tile and (b) a circular tile. . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Thermal optimization simulation setup. . . . . . . . . . . . . . . . . 58 Quadratic ground plane profiles. (a) Zero edge thickness. (b) Equal volume. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Varying ground thickness for each of the thermal conduction improvement schemes. . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Expected temperature as a function of power per chip, all ground leveling schemes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 IC temperature as a function of power per chip for different ground metal volume, "equal volume" approximation. . . . . . . . . . . . . . 60 Estimated temperature of tile with PV and RFIC heat sources in space. 61 A basic rectenna design. . . . . . . . . . . . . . . . . . . . . . . . . 61 A top-level schematic of the SSP RFIC. . . . . . . . . . . . . . . . . 64 An RFIC centralized 2.5GHz output phase locked loop (PLL). . . . . 64 An RFIC delay-locked loop (DLL). . . . . . . . . . . . . . . . . . . 65 Second ×4, 2.5 GHz to 10 GHz clock-multiplier unit (CMU). . . . . 65 CMU phase shift mechanism (Fig. courtesy of Dr. B. Abiri). . . . . . 66 Block diagram of the power generation quadrature. . . . . . . . . . . 66 Power amplifier block diagram. . . . . . . . . . . . . . . . . . . . . 67 Block diagram of four PAs stacked on top of each other from DC perspective [73]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Block diagram of an RFIC with two output PAs stacked from a DC perspective [74]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Die photo of the phased array transmitter RFIC. . . . . . . . . . . . . 69 xiii 3.33 3.34 3.35 3.36 3.37 3.38 3.39 3.40 3.41 3.42 3.43 3.44 3.45 3.46 3.47 3.48 3.49 3.50 3.51 3.52 3.53 Length variations due to (a) reference distribution routing and (b) output antenna traces. . . . . . . . . . . . . . . . . . . . . . . . . . Conceptual inter-tile communication and reference distribution (Fig. courtesy of Dr. F. Bohn). . . . . . . . . . . . . . . . . . . . . . . . . Clock distribution to CMOS-driven phased array. . . . . . . . . . . . On-chip reference generation and distribution (daisy chain option) (Fig. courtesy of Dr. F. Bohn). . . . . . . . . . . . . . . . . . . . . . Phased array loss of efficiency due to the array’s phase noise (infinite array approximation) (Fig. courtesy of Dr. F. Bohn). . . . . . . . . . Hybrid DLL function. (a) Schematic and (b) hybrid phase tracking. . Circuit description of the (a) overflow detector/actuator, (b) DCDL MUX set, and (c) reset circuits for a hybrid operation. . . . . . . . . Hybrid delay line structure. . . . . . . . . . . . . . . . . . . . . . . PLL VCO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A variable loop filter for the optimization of the PLL noise performance at different frequencies. . . . . . . . . . . . . . . . . . . . . . Reference spur sources: (a) Charge pump mismatch and (b) DC current leakage. Periodic charge transients on control voltage line (c) due to up/down mismatch and (d) DC leakage. . . . . . . . . . . . . Pass-through switch structure for up/down mismatch spur prevention. PLL die micrograph. . . . . . . . . . . . . . . . . . . . . . . . . . . PLL spur reduction switch measurement. . . . . . . . . . . . . . . . PLL reference spur levels for different digital settings of start/stop times of the pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL phase noise PSD measurement vs. simulation . . . . . . . . . . Hybrid DLL die photo. . . . . . . . . . . . . . . . . . . . . . . . . . Hybrid lock process at different time scales. (a) Loop filter control voltage, (b) time delay between reference and output clocks, and (c) time domain waveforms (adjusted). . . . . . . . . . . . . . . . . . . Cascaded PLL and DLL measurement setup. . . . . . . . . . . . . . Noise performance. (a) 50MHz DLL phase noise and rms jitter, and (b) 2.5GHz post PLL phase noise and rms jitter. The red curves are the rms measurement uncertainty. . . . . . . . . . . . . . . . . . . . Performance vs. frequency. (a) Participating DCDL cell count, (b) power consumption of participating DLL blocks, and (c) rms jitter within the 1kHz - 10MHz band. . . . . . . . . . . . . . . . . . . . . 70 71 71 72 73 75 76 77 77 77 78 79 79 80 81 82 83 84 84 85 85 xiv 3.54 3.55 3.56 3.57 3.58 3.59 3.60 3.61 3.62 3.63 3.64 3.65 3.66 3.67 3.68 3.69 3.70 3.71 3.72 3.73 3.74 3.75 3.76 Cascaded DLL jitter (a) test setup and (b) photo. . . . . . . . . . . . 86 Cascaded DLL jitter. (a) 1kHz - 10MHz measurement, and (b) 1kHz- 𝑓𝑟𝑒 𝑓 /2 measurement. Red and blue curves indicate locking to inverted/non-inverted output, respectively. . . . . . . . . . . . . . . . 87 RFIC output: (a) power and (b) phase shift range [84]. . . . . . . . . 88 RFIC single channel output phase-noise PSD (Fig. courtesy of Dr. F. Bohn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 A flexible phased-array transmitter unit-cell (tile). . . . . . . . . . . 90 Multiple tile unit-cells combined on the same flexible laminate to form a larger array. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Chip-board interface with a small rigid interposer. . . . . . . . . . . 91 Chip interposer measuring (a) return loss and (b) insertion loss. . . . 91 Bandwidth, directivity, radiation resistance, and efficiency with respect to surface waves excitation for a resonant square element as a function of dielectric thickness for different 𝜖𝑟 [85]. . . . . . . . . . . 92 Vacuum-suspended patch antenna: (a) designed and (b) fabricated/measured [84]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Flexible patch antenna pattern [84]. . . . . . . . . . . . . . . . . . . 93 Flexible patch antenna sheet and feed above ground. . . . . . . . . . 94 Antenna packing curvature limit due to different radii of the two flexible sheets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Simulated change in element pattern when placed in a finite-size array with a finite ground plane. . . . . . . . . . . . . . . . . . . . . . . . 95 Vertical sheet antenna concept. . . . . . . . . . . . . . . . . . . . . 96 Vertical sheet antenna (a) test structure (the plastic support should be removed or changed in the final design), (b) input matching, (c) antenna pattern 0◦ , (d) antenna pattern 90◦ . . . . . . . . . . . . . . . 97 Collapsible spiral spring concept. . . . . . . . . . . . . . . . . . . . 97 Collapsible spring antenna (a) test structure (the plastic support should be removed or changed in the final design), (b) input matching, (c) antenna pattern 0◦ , (d) antenna pattern 90◦ . . . . . . . . . . . . . 98 Fabrication options for a flexible 4-layers PCB. . . . . . . . . . . . . 99 Array pattern measurement setup. . . . . . . . . . . . . . . . . . . . 101 Simulated phase of each antenna output for broadside radiation [84]. . 102 Array broadside pattern [84]. . . . . . . . . . . . . . . . . . . . . . . 102 Broadside array fields recorded in 2-D [84]. . . . . . . . . . . . . . . 103 xv 3.77 3.78 3.79 3.80 3.81 3.82 3.83 3.84 3.85 3.86 3.87 3.88 3.89 3.90 3.91 3.92 4.1 4.2 4.3 4.4 4.5 Steered beam pattern (a) up and (b) left [84]. . . . . . . . . . . . . . 104 Phased array transmitter tile broadside hologram shows the evolution of the radiated field in space [84]. . . . . . . . . . . . . . . . . . . . 105 Phased array transmitter tile EIRP (image reproduced from [84]). . . 106 Integrated tile: (a) structure and (b) PV reflector concept. . . . . . . . 107 Integrated RF-PV tile. (a) Completed demonstration board, (b) antenna sheet, and (c) weight of the assembled board. . . . . . . . . . . 107 Testing an integrated RF-PV tile under AM0 light source. (a) Measurement setup, (b) demonstration of RF lighting an indicator LED. (c) Power is not transferred when line-of-sight is lost. . . . . . . . . . 108 An assembled flexible phased array transmitter. . . . . . . . . . . . . 110 Power strap and supply interface for the flexible phased array transmitter.111 Antenna sheets: (a) a raw sheet and (b) a close-up on the board interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Antenna sheet assembly. (a) Schematic description and (b) a demonstration of the assembly process. . . . . . . . . . . . . . . . . . . . . 113 The challenges in calibration of large arrays. (a) Physical problem setup and (b) implication on receiver dynamic range. . . . . . . . . . 113 Selecting groups of elements for phased array calibration/focusing: (a) half the array elements and (b) fourth of the array elements. (c) An example for a selection of groups of elements in a 16-element array to span an orthogonal phase space. . . . . . . . . . . . . . . . 114 Phased array focusing setup (left) and results (right). . . . . . . . . . 114 Antenna pattern of a steered phased array beam: (a) Broadside, (b) up, (c) down, (d) right, and (e) left. . . . . . . . . . . . . . . . . . . 116 A flexible phased array transmitter: (a) flat and (b) deformed. . . . . 117 Deformation correction. (a) Focusing, (b) deformation, and (c) refocusing of a deformed flexible phased array transmitter. . . . . . . . 117 High frequency clock distribution schemes: (a) RF based and (b) laser based. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Laser clock distribution block diagram. . . . . . . . . . . . . . . . . 121 Comparison of distribution network power loss for different distribution schemes at (a) 28GHz and (b) 10GHz. . . . . . . . . . . . . . . 123 Counting the (a) total length of reference distribution lines and (b) distance from centralized source to a single IC. . . . . . . . . . . . . 124 Optical reference chip top block diagram. . . . . . . . . . . . . . . . 125 xvi 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 Small signal model of a CMOS PD (recreated from [106]). . . . . . . 126 A cross section of doping concentrations for PD design (Fig. courtesy of C. Ives). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Photodiode (a) capacitance density and (a) responsivity simulations (Figs. courtesy of C. Ives). . . . . . . . . . . . . . . . . . . . . . . . 127 Photodiode layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Input chain schematics (Fig. courtesy of C. Ives) . . . . . . . . . . . 128 PD LNA with a gain-boost −𝑔𝑚 cell (Fig. courtesy of C. Ives). . . . . 129 A common-mode stabilized inverter amplifier (Fig. courtesy of C. Ives). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Transient simulation of the input chain’s output (Fig. courtesy of C. Ives). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 An ×8, 3.5 GHz to 28 GHz PLL schematic . . . . . . . . . . . . . . 130 VCO and ILFD schematics. . . . . . . . . . . . . . . . . . . . . . . 131 PLL intermediate and last stage divide-by-2 circuits. (a) A general structure of a differential frequency divider, (b) CML logic for 14 GHz to 7 GHz division, and (c) TSPC logic for 7 GHz to 3.5 GHz division. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 PLL ILFD lock range alignment with the VCO control voltage. . . . . 132 28GHz PLL simulation of (a) transient VCO control voltage and (b) transient jitter. Estimated jitter is ≈ 60 fs. . . . . . . . . . . . . . . . 133 Output channel vector modulator phase shifter schematic. . . . . . . 133 Vector modulator phase shifter. (a) Small signal gain and (b) transient phase shift simulations. . . . . . . . . . . . . . . . . . . . . . . . . . 134 Power amplifier output schematic. . . . . . . . . . . . . . . . . . . . 134 Output power amplifier. (a) Small signal gain simulation and (b) transient supply and RF output swing simulation. . . . . . . . . . . . 135 Optical reference distribution chip die photo. . . . . . . . . . . . . . 136 xvii LIST OF TABLES Number Page 2.1 Comparison table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1 Average worldwide prices for electrical power∗ . . . . . . . . . . . . 37 3.2 Estimated values for 𝐿𝐶𝑂𝐸 𝑆𝑆 calculation . . . . . . . . . . . . . . . 43 3.3 Estimated values for 𝐿𝐶𝑂𝐸 𝑆𝑆 calculation . . . . . . . . . . . . . . . 44 3.4 Estimated values for 𝐿𝐶𝑂𝐸 𝑆𝑆 calculation . . . . . . . . . . . . . . . 45 3.5 Breakdown of mass contributions and total mass of a 10 cm × 10 cm tile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.6 Mass breakdown of a 60 m × 60 m spacecraft . . . . . . . . . . . . . 55 3.7 Expected improvement in areal mass between SSP iterations . . . . . 55 3.8 Optimization values of variable PLL loop filter and charge-pump current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.9 DLL noise performance, based on Fig. 3.55. . . . . . . . . . . . . . 86 3.10 DLL performance comparison table . . . . . . . . . . . . . . . . . . 88 3.11 Measured (simulated) pattern data for broad-side beam (𝜑 = 0◦ , 𝜃 = 0◦ ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.12 Measured (simulated) pattern data for left-steering (𝜑 = 0◦ , 𝜃 = 30◦ ) 104 3.13 Measured (simulated) pattern data for up-steering (𝜑 = 90◦ , 𝜃 = 30◦ ) 105 4.1 Calculated quantities of reference distribution power dissipation. . . . 124 xviii NOMENCLATURE CMOS. silicon complementary metal-oxide semiconductor. EIF/EOF. "Operation Iraqi/Enduring Freedom" - An acronym that refers to the U.S.-led conflict in Afghanistan and Iraq. EM. Electromagnetic. GEO. Geosynchronous equatorial orbit at an altitude of 35,000 km (22,000 miles) above earth. IC. Integrated Circuit. ILFD. Injection-Locked Frequency Divider. JP8. Jet propulsion fuel, specified and used widely by the US military. LCOE. Levelized Cost of Electricity. LEO. Low earth orbit at an altitude between 160 to 2,000 km (99 to 1,200 miles) above earth. LNA. Low Noise Amplifier. PA. Power Amplifier. PD. Photo Diode. PLL. Phase-Locked Loop. PPF. Poly Phase Filter. PS. Phase Shifter. PSD. Power Spectral Density. PV. Photovoltaic. RFIC. Radio Frequency Integrated Circuit. SBP. Space Based Power. SSP. Space Based Solar Power. TIA. Transimpedance Amplifier. VCO. Voltage Controlled Oscillator. 1 Chapter 1 INTRODUCTION Had we told a mid-19th century scholar that within a hundred years our life expectancy would more than double, that a man would walk on the moon, and that we would be able to light entire cities by the flip of a switch, he would have laughed in our face, called us madmen, or at least asked for some of that recreational substance we had been consuming after the siesta. Yet within a century, humankind achieved all those and more: Our food production has increased by an order of magnitude, we drive cars that are faster than a cheetah and can go over a longer distance, and we are able to respond and combat new diseases at an admirable speed through a truly global collaborative effort. This last achievement is one that we are currently experiencing as the COVID-19 pandemic threatens to hurt millions around the globe and paralyze economy and society alike. All of these remarkable achievements have one thing in common: they have been enabled by the technological breakthroughs of mathematicians, physicists, chemists, biologists, engineers, and other highly skilled professionals. Technology, however, is necessary but insufficient for a discovery to change the world. A key ingredient in the process is its democratization - or scaling, in the scientific jargon - which is the process by which it is made accessible for the general public’s use. We light our homes and operate our household items because the cost of a light-bulb is around one dollar and electricity is cheaper than a quarter for a kWh. We are not starving because a pound of rice can be produced and sold for a few dozen cents, and we can battle viral infections because we can manufacture and disseminate hundreds of millions of vaccines globally. In this regard, it appears that there has never been an enabler of scaling in the history of electronics quite like the integrated circuit, which allows to reliably mass-produce complex, miniaturized systems. Of these, silicon complementary metal-oxide semiconductor (CMOS) fabrication processes deserve a place of honor. While they do not offer the highest performance, the low cost of fabrication and rapid shrinking of technology nodes deliver an astounding value in cost-to-complexity ratio. Not only can complete systems and networks (SoCs, NoCs) be implemented on a single chip, but also CMOS ICs enable the realization of previously unfeasible 2 and uneconomical architectures. This thesis summarizes my work at Caltech on two such types of systems: magnetic biosensors and flexible, very large-scale phased arrays. Though seemingly disconnect, they are both fantastic examples of the way that CMOS integrated circuits enable the scaling of electronic systems in several contexts to create paradigmshifting architectures. Integrated biosensors can be fabricated at low cost to offer multi-modal, multi-channel building blocks for on-site diagnostics and mass producible analysis instruments. One great advantage is that their signal conditioning and processing circuitry can be integrated on-chip not only to reduce their size, cost and power consumption, but also to allow modalities that are impractical otherwise, such as very high frequencies of operation. Very large-scale phased arrays, on the other hand, must utilize highly mass-producible technologies in order to be rendered suitable for most consumer applications. In particular, phased arrays implemented on flexible substrates are arguably unfeasible without taking advantage of highly functional parts, capable of self synchronization, calibration and regulation. This, to account for vibrations and deformation with a small component count to maintain the system’s physical flexibility. While a large part of the thesis body deals with the design of radio-frequency integrated circuits, it is important to note that substantial attention is given to the fundamental justification of the concepts and to quantitative system-level considerations. This is done for two reasons. First, as an engineer, I believe that systems should be designed to be both sound and useful. Second, both biosensors and large phased arrays require a high level of precision, for example in the sensitivity of a sensor or in the quality of a clock synchronizing numerous array elements. These can only be achieved with a deep understanding of quantitative considerations which should not be oversighted. For these reasons, each of the thesis chapters start with a substantial theoretical background, putting it in the context of the field to which it pertains. The thesis organization is as follows: the first chapter studies the underlying physics of inductance shift sensors as a special case of the broader family of magnetic energy deviation sensors. The result is a quantitative definition of performance metrics with all assumptions and approximations explicitly stated. The analysis is then used to design a modified ac Wheatstone bridge that uses two inductor pairs in a cross-coupled configuration, to half its size and double its transducer gain while maintaining a fully differential structure with a matched frequency response. Finally, 3 the measurements of a proof-of-concept sensor are presented and discussed. The second chapter presents my work on very-large scale arrays as a part of Caltech’s solar-space power program (SSPP). First, an analysis of the economics of solarspace power is presented and its implications discussed. Then, an overview of the proposed SSPP architecture is given. Later, three levels of the work of the SSPP RF-electronics group - with my contribution as a part of it - are presented: First, a phased array driver RFIC is presented, which is at the heart of the energy conversion system to perform most of the system’s task in a cost-effective and modular fashion. Second, the RFIC is used to design a scalable and modular RF-photovoltaic power conversion phased array unit-cell on a flexible PCB substrate. And lastly, sixteen of these unit cells patterns are combined to build a single-sheet, flexible, 256-elements phased array. The third and final chapter presents a novel approach to synchronize RF phased arrays with a laser. It discusses the theoretical background and the quantitative trade-offs of several clock synchronization schemes. A novel mm-wave phased RFIC with an integrated photodiode for clock synchronization purposes is then presented. Notably, this section discusses only the RFIC simulated expected performance, since the chips were just recently fabricated and were not yet measured. I wish the readers to enjoy reading through this thesis, and I hope that they will find it interesting and inspiring. 4 Chapter 2 ANALYSIS AND DESIGN OF MAGNETIC ENERGY-DEVIATION SENSORS Magnetic sensors are often proposed as a miniaturized, low-cost alternative to fluorescence for cell-sorting and on-site diagnostics applications [1][2]. Many of these systems sense changes in relative permeability to detect biological material bound to magnetic particles (beads) within the sensing area. The integration of susceptibility sensors on a single chip is appealing since it offers mass-producibility and allows the addition of significantly more complex functionality in comparison to discrete solutions. A major challenge with on-chip implementations, however, is the required sensitivity. For instance, cytometers need to be able to detect single cells[3], and hand-held diagnostics devices might have to sense concentrations as small as a few parts per million of material in a sample [4]. So far, the most sensitive devices demonstrated have used inductors as a magnetic sensor, with different tradeoffs. Frequency shift oscillators [5] are compact and have the highest sensitivity, but suffer from oscillator long-term drift [6][7]. Integrated transformers on the other hand [8][9] are more suitable for cell sorting applications, but use additional tuning inductors to achieve their required single bead sensitivity. In addition, the physical implementations of these systems rely on an intuitive approach, often with only qualitative prediction of performance metrics. This chapter presents a more quantitative method. First, a deeper understanding of the underlying physics of susceptibility sensors is developed, which provides a systematic design technique and allows to discuss the special case of inductive shift sensing with all assumptions and approximations explicitly stated. Then, several types of inductive shift sensors will be presented, including a novel sensor based on a compact differential coupled inductive bridge. Later, the new sensor topology will be presented, and it will be shown how it offers a response time similar to transformer-based sensors and a sensitivity comparable to frequency shift oscillators. Finally, an on-chip coupled bridge integrated sensor will be demonstrated alongside a quantitative discussion of measurement results. 5 V0 , B0 =µ0H0 V0 , B =µ0H J0(r) Vp B, H J(r) (a) (b) Figure 2.1: Arbitrary current density in volume 𝑉0 (a) with, and (b) without a magnetic particle 𝑉𝑝 in the volume. 2.1 Magnetic Susceptibility Sensors Magnetic susceptibility sensors are designed to sense changes in the relative permeability in space. Traditionally, they are regarded as inductors with an inductance that shifts in the presence of magnetic material. While useful for practical circuit design, this viewpoint obscures the true nature of those devices and might limit designers to a specific subset of physical implementations. Fundamentally, susceptibility sensors are magnetic energy storage elements and the sensed quantity is the change in stored magnetic energy due to a magnetic perturbation. Magnetic energy deviation sensors A magnetic sensor can be thought of as an arrangement of current densities 𝑱0 (𝒓), as in Fig. 2.1a (bold variables are vectors). These currents induce a magnetic field 𝑩0 (𝒓) in the volume 𝑉0 , which stores magnetic energy, 𝑈𝐵0 , of 1 𝑈𝐵0 = 2 ∫ 𝑯0 · 𝑩0 𝑑𝑣. (2.1) 𝑉0 If the medium is isotropic and 𝑩0 is linear with respect to 𝑯0 , the two can be related by 𝑩 0 = 𝜇 0 𝑯0 . (2.2) We now introduce a magnetic particle, with volume 𝑉𝑝 into 𝑉0 (Fig. 2.1b). In general, the original currents and fields will change their value to 𝑱(𝒓), 𝑩(𝒓), and 𝑯(𝒓) in order to fulfill Maxwell’s equations in its presence. The modified stored magnetic energy 𝑈𝐵 can then be found from solving Maxwell’s equations again and applying the new fields to (2.1). However, if we assume that the current distribution 𝑱0 (𝒓) is far away enough such that it does not change significantly in the presence of the added particle, and that the particle was unmagnetized before it was entered to 𝑉0 , an approximate solution is given in [10]. Suppose that before 𝑉𝑝 was introduced 6 into 𝑉0 , the currents 𝑱0 (𝒓) in Fig. (2.1a) were reduced to 0. Then, with 𝑉𝑝 in 𝑉0 , those currents are increased back until 𝑱(𝒓) = 𝑱0 (𝒓). The work 𝑊 done to recreate 𝑱0 (𝒓) is ∫ 𝑩 ∫ 𝑊= 𝑯 · 𝑑 𝑩, 𝑑𝑣 (2.3) 0 𝑉0 and the excess energy stored by the particle is Δ𝑈𝐵 = 𝑊 − 𝑈𝐵0 . (2.4) Substituting (2.1) and (2.3) into (2.4) and separating integrals leads to 1 Δ𝑈𝐵 = 2 ∫ (𝑯 · 𝑩 − 𝑯0 · 𝑩0 )𝑑𝑣 𝑉0 −𝑉 𝑝 ∫ 𝑩 ∫ + 𝑑𝑣( 𝑉𝑝 0 1 𝑯 · 𝑑 𝑩 − 𝑯0 · 𝑩0 ). 2 (2.5) Assuming that (2.2) holds and using boundary conditions [10] shows that the integration over (𝑉0 − 𝑉𝑝 ), outside the particle, is proportional to an integral over 𝑉𝑝 . Furthermore, by neglecting hysteresis effects and assuming that inside 𝑉𝑝 , 𝑩 = 𝜇𝑯, the change in stored magnetic energy can be written as 1 Δ𝑈𝐵 = 2 ∫ 𝑴 · 𝑩0 𝑑𝑣. (2.6) 𝑉𝑝 It is noteworthy that the stored magnetic energy due to a magnetic particle in space depends only on 𝑴 (𝒓), the magnetic polarization, and 𝑩0 (𝒓) inside 𝑉𝑝 . This sets the theoretical foundation to analyze magnetic susceptibility sensors. Energy deviation induced by magnetic nanoparticles Magnetic beads are made of ferromagnetic nano-scale particles embedded in a non-conductive matrix. Even though their internal structure can be complex and vary between manufacturers, they are commonly modeled and characterized as paramagnetic material[11][12], where, for weak magnetic fields, 𝑩 𝒑 = 𝜇 𝑝 𝑯 𝒑 = 𝜇0 (1 + 𝜒)𝑯 𝒑 . (2.7) Here 𝜇0 is the vacuum permeability, 𝜒 is the bead effective (unit-less) susceptibility, and subscript 𝑝 refers to the region inside the particle. Since the magnetic properties 7 stem from ferrites, 𝜒 is typically ∼10−1 , orders of magnitude larger than regular paramagnetic materials. The phenomenon is referred to as superparamagnetism. A magnetic bead will be magnetized if placed in a static, constant magnetic field 𝑩0 (𝒓), and 𝑴 (𝒓) is calculated in [13] to be 𝑴= 3 𝜇 𝑝 − 𝜇0 ( ) 𝑩0 . 𝜇0 𝜇 𝑝 + 2𝜇0 (2.8) It is noteworthy that integrated magnetic sensors usually operate at radio frequencies where the electromagnetic fields are not static. However, their inductors are usually designed with dimensions much smaller than wavelength so they can be modeled as lumped elements and treated with a quasi-static approximation [14]. Even though integrated inductors store electric energy, manifested as parasitic capacitance, the phenomenon occurs mostly between the inductor surface and the bulk, whereas magnetic particles interact with the sensor above the chip surface. Therefore, the validity of (2.8) will be assumed for the following treatment. If placed in an energy storage deviation sensor as defined in 2.1, the energy shift due to a magnetic bead can easily be calculated by substituting (2.8) into (2.6). If the bead is small enough such that the unperturbed magnetic field in its proximity is roughly constant, the integral can be simplified to Δ𝑈𝐵 ≈ 1 3 𝜇 𝑝 − 𝜇0 ( )|𝐵0 | 2𝑉𝑝 2 𝜇0 𝜇 𝑝 + 2𝜇0 (2.9) with |𝐵0 | 2 due to the vector dot product in (2.6). This result can be written in terms of 𝜒 and the magnetic energy density of the un-perturbed system, 𝑢 𝐵0 = |𝐵0 | 2 /2𝜇0 , as 3𝜒 Δ𝑈𝐵 ≈ ( )𝑢 𝐵0𝑉𝑝 . (2.10) 𝜒+3 It is important to note that even though 𝑢 𝐵0 is considered constant in the proximity of the bead, it might still vary in space, as will become clear in 2.1. Inductance shift sensors As a special case, we can define the current densities 𝑱0 (𝒓) as an assortment of current-carrying wires, 𝐼 𝑘 (Fig. 2.2) and define Δ𝑈𝐵 in terms of the change in 𝐿 and 𝑀, the self- and mutual- inductances associated with each wire-pair. Under harmonic excitation in the quasi-static approximation, 𝐾 wires store magnetic energy 8 of 𝐾 Õ 𝐾 𝐾 Õ 1Õ 2 𝐿 𝑘0 𝐼 𝑘 + 𝑀𝑘0,𝑙0 𝐼 𝑘 𝐼𝑙 , 𝑈𝐵0 = 2 𝑘=1 𝑘=1 𝑙=𝑘+1 (2.11) where 𝐿 𝑘0 , 𝑀𝑘0,𝑙0 are their unperturbed self-, and mutual-inductances. The deviation in the stored magnetic energy is then proportional to the sum of all of the partial deviations Δ 𝐿 𝑘 , Δ 𝑀𝑘,𝑙 , the change in 𝐿 𝑘0 , 𝑀𝑘0,𝑙0 , respectively, scaled by the current intensities, 𝐼 𝑘 : ( 𝐾 Õ 𝐾 𝐾 Õ 3𝜒 1Õ Δ 𝑀𝑘,𝑙 𝐼 𝑘 𝐼𝑙 . Δ 𝐿 𝑘 𝐼 𝑘2 + )𝑢 𝐵0𝑉𝑝 ≈ 𝜒+3 2 𝑘=1 𝑘=1 𝑙=𝑘+1 (2.12) This result suggests that the spatial response profile of a magnetic energy deviation sensor may be engineered by appropriately arranging the generating current configuration. Exemplary synthesis objectives are maximizing the total deviation for a given power input, or producing a spatial uniform response, either on a surface or vertically along a microfluidic channel. A special case of (2.12) is when the arbitrary wire configuration in Fig. 2.2 consists of a single wire. Then, 𝐼1 = 𝐼 and 𝐼2 ...𝐼 𝑘 ...𝐼𝐾 = 0, and the inductance shift is calculated to be Δ𝐿 ≈ 2 3𝜒 ( )𝑉𝑝 𝑢 𝐵0 . 𝐼2 𝜒 + 3 (2.13) Interestingly, for typical superparamagnetic materials, 𝜒  3, so Δ𝐿 ≈ 2 𝜒𝑉𝑝 𝑢 𝐵0 . 𝐼2 (2.14) A similar result was previously presented in [15] assuming only that the magnetic field, 𝑯0 (𝒓), does not change in the presence of a small magnetic perturbation. Here we have shown how the latter holds only for small values of 𝜒 and only if the fundamental assumptions of 2.1 are fulfilled. V0 V0 B0 , uB0 B0 , uB0 Vp , χ I2 ... In,0 (a) I1 Ik IK (b) Figure 2.2: Magnetic bead with volume 𝑉𝑝 and susceptibility 𝜒 in a space 𝑉0 with an unperturbed magnetic energy density of 𝑢 𝐵0 = 𝐵02 /2𝜇0 . 9 I1 =…=IN =I ^ z IN I1 ^ 𝜙 ^ ρ I I Inductor Trace Cross-Section In,1 In,m In,M I=∑ In,m m Figure 2.3: Planar inductor segmentation as one-dimensional current-loops. Magnetic field of a planar spiral inductor Since 𝑉𝑝 and 𝜒 are known physical properties, the only information needed to define an inductor based magnetic-sensor response is its unperturbed energy density profile. Without loss of generality, we consider an 𝑁-turn octagonal inductor, and approximate it as an assortment of concentric circular loops, as shown in Fig 2.3. Each turn is modeled as 𝑀 parallel one-dimensional loops, carrying currents of 𝐼𝑛,𝑚 = 𝐼 · 𝑓𝑛,𝑚 , (1 ≤ 𝑚 ≤ 𝑀, 1 ≤ 𝑛 ≤ 𝑁). Although the currents in all the turns are equal (𝐼1 ...𝐼 𝑁 = 𝐼) for inductors modeled as lumped components, the current distributions inside each of the turns generally are not, due to the skin effect, current crowding, or such. 𝑓𝑛,𝑚 is an arbitrary scaling factor that was added in order to capture these secondary interactions. The magnetic field, 𝑩𝑛,𝑚 , generated by each loop can be derived analytically from [13][16], and is most easily described in cylindrical coordinates. Due to the structural symmetry in 𝜙, it depends only on the vertical and radial coordinates 𝑧 and 𝜌, respectively, and has the following vector components: 𝐼𝑛,𝑚 (𝜆 𝜌 𝝆ˆ + 𝜆 𝑧 𝒛ˆ) 𝜇0 · , p 2𝜋 [𝑧2 + (𝜌 − 𝑎 𝑛,𝑚 ) 2 ] 𝑧2 + (𝑎 𝑛,𝑚 + 𝜌) 2 (2.15) 𝑧 [(𝑎 2𝑛,𝑚 + 𝑧2 + 𝜌 2 )𝐸 2 (𝑘) − 𝐸 1 (𝑘)], 𝜌 (2.16) 𝜆 𝑧 = [(𝑎 2𝑛,𝑚 − 𝑧2 − 𝜌 2 )𝐸 2 (𝑘) + 𝐸 1 (𝑘)], (2.17) 𝑩𝑛,𝑚 (𝜌, 𝑧) ≈ with 𝜆𝜌 = 10 and 𝜌 · 𝑎 𝑛,𝑚 𝑘2 = 4 2 , 𝑧 + (𝑎 𝑛,𝑚 + 𝜌) 2 (2.18) where 𝑎 𝑛,𝑚 is the loop radius, 𝐸 1 (𝑘), 𝐸 2 (𝑘) are elliptic functions of the first and second kinds, respectively, and 𝒛ˆ, 𝝆ˆ are the vertical and radial field orientations, respectively. The total field of the inductor is the sum of all the fields that are generated by all the loops in all the traces: 𝑩(𝜌, 𝑧) ≈ 𝑓𝑛,𝑚 (𝜆 𝜌 𝝆ˆ + 𝜆 𝑧 𝒛ˆ) 𝜇0 𝐼 Õ . p 2𝜋 𝑛,𝑚 [𝑧2 + (𝜌 − 𝑎 𝑛,𝑚 ) 2 ] 𝑧 2 + (𝑎 𝑛,𝑚 + 𝜌) 2 (2.19) An important result of this calculation is that the magnetic field 𝑩 is proportional to the inductor current, 𝐼. Hence, 𝑢 𝐵 ∝ 𝐼 2 , and the inductance shift in (2.13) is to the first order independent of the excitation current. In practice, setting 𝑓𝑛,𝑚 = 1/𝑀 leads to a very good estimate of the field components and the calculated magnetic fields are remarkably similar to full-3D EM simulations, even when octagonal inductors are approximated as circular, as shown in 2.4. This allows for a rapid a priori quantitative estimate of an inductance-shift sensor sensitivity. 2.2 A Survey of Integrated Magnetic Biosensors To date, three types of integrated inductance shift sensors were demonstrated: frequency shift sensors, transformer-based sensors, and bridge sensors. The first type detects the change in the frequency of a free-running oscillator, while the other two detect voltage offsets induced by magnetic perturbations above the sensor surface. As such, the first type is a time varying system while the other two are LTI for analysis purposes. It is noteworthy that the most of the systems surveyed here were designed intuitively, with a limited physical background to estimate their performance. Therefore some of their issues, which will be discussed, are not fundamental flaws but stem from uninformed design choices. Frequency shift sensors A frequency shift oscillator senses changes in the permeability of the environment by monitoring its self-oscillating frequency. These sensors are usually modeled as an 𝐿𝐶 tank in which 𝐿 is the sense inductor and 𝐶 is the effective parallel tank capacitance. In this model, the positive feedback mechanism of the oscillator is lumped into a negative resistance block as shown in Fig. 2.4 to obtain the oscillation frequency 1 𝑓0 = √ . (2.20) 𝐿 0𝐶0 11 This architecture is advantageous due to its simplicity. Practical implementation of LC oscillators is well-studied and resolving the frequency shift requires nothing but a digital counter if the signal amplitude is large enough. The digital output of the system eliminates the need for additional interface circuitry to a processing unit. The relation between the shift in the oscillation frequency and environment permeability (modeled as additional inductance) is resolved to the first order from (2.20) and is conveniently independent of the oscillation amplitude   Δ𝐿 𝑓 = 𝑓0 1 − . (2.21) 2𝐿 The two main drawbacks of these systems are their limited noise performance and relatively slow response time. Measuring the frequency shift with a digital counter requires by definition a gating clock to trigger the counter, effectively imposing a lower-bound on the system accuracy. Typical magnetic nano-particles are responsive in the low-GHz range and therefore sensing particle-related sub-ppm frequency shifts requires by definition gating times in the order of milliseconds. Worse still, since these are free running oscillators, the timing accuracy is limited by their phase noise [17], and hence averaging is only useful to a certain extent. Several variations were proposed to overcome these issues: Differential structures and correlated double counting schemes [15][18] employ dummy devices to cancel out local drifts in integrated sensors. While they show a significant improvement in sensitivity both theoretically and practically, they still require several seconds of averaging to achieve these performance. Long-term drifts due to temperature gradients and signal coupling far degrade the stated performance in measurements lasting more that 90 seconds. Recently a dual-mode oscillator sensor topology was proposed [7]. By using the same inductor core at two different frequencies, namely where the magnetic particles are responsive and where they are not, temperature drifts are cancelled to a significant extent for very long time periods. This sensor is however -gm C (a) L -gm C L+ΔL (b) Figure 2.4: An oscillator circuit (a) with and (b) without a magnetic perturbation in the inductor core. 12 targeting by design a single type of magnetic nanoparticles and relies on accurate knowledge of their frequency response, which might vary between manufacturers or different batches [15]. Frequency shift sensors demonstrate the highest reported sensitivity do date, but their relatively slow response time makes them unsuitable for dynamic applications such as cell-cytometry. Transformer based sensors Transformer-based permeability sensors are linear transducers. They sense changes in the magnetic flux coupled from the primary ("excitation") coil of a transformer to its secondary ("pickup") coil. A simplified implementation is shown in Fig. 2.5. The excitation coil is wound around the core in a "figure-8" shape so in the absence of perturbation the total flux change in the secondary is zero. Magnetic particles placed around the excitation coil interfere with the flux coupling between the primary and secondary, and thus induce either a positive or a negative signal in the output amplifier. This topology is fundamentally different than the frequency shift scheme. Its main advantage is that the transducer can be described as an LTI system and the front-end consists of driven amplifiers. At a low GHz range, these sensors work far above the /1 𝑓 noise corner and the transducer noise contribution is only the thermal noise of the equivalent series resistors of the transformer’s inductors. The lack of selfoscillating noise components 1/ 𝑓 𝑛 allows to integrate it for longer time periods and trade bandwidth with SNR. The drawback of this architecture is its complexity. The coupled signals can be small (in the orders of microvolts) and therefore require substantial amplification which itself adds noise and is subject to drift. The sensed RF signal needs to be down-converted and digitized for further processing. Practically, the added noise and interference are far greater than the fundamental sensitivity limit of the linear transducer. While this is a technology-dependent issue, it is the reason Vin M Vout Lexc Lpickup Figure 2.5: An example of a magnetic perturbation travelling in the vicinity of a transformer-based inductance-shift sensor. 13 why transformer-based sensors have so far demonstrated slightly lower sensitivity than their frequency counting counterparts. Bridge sensors Bridge sensors are another type of linear transducers. Unlike transformers, their excitation is not coupled to the output, but drives a balanced impedance at the input of a receiver amplifier. A perturbation of the balance generates a deviation from the amplifier quiescent point and thus can be detected. Bridge circuits are well-studied. They usually employ a differential architecture to null common-mode perturbation that might overshadow the sensed quantity. AC bridges are commonly used for precision measurements [19], and therefore are natural candidates for biomedical magnetic sensing systems. Moreover, capacitive and resistive bridges were demonstrated with complementary sensing elements [20][21] in which both bridge branches respond to a perturbation with inverse polarity to double the differential output voltage. Inductive bridges are more challenging, however, and the problem is exacerbated in integrated implementations. An all-inductor bridge requires four inductors, is large, and suffers from unwanted coupling effects. Reducing its size by changing one of its branches with capacitors is also problematic as it leads to an unmatched frequency response and to a narrow-band nulling. The next section will describe a novel bridge architecture which takes advantage of the mutual coupling of two coupled inductors to reduce its size while maintaining a matched frequency response. As a result, its differential-output voltage also increases compared to a standard structure. 2.3 Coupled Inductive Bridge Sensors Transducer gain The sensor in Fig. 2.6a is based on a differentially driven, differential AC bridge, but is composed of two pairs of coupled inductors. A perturbation of the effective permeability in core 𝐴, for example, (Fig. 2.6b) incurs shifts of Δ 𝐿 1 , Δ 𝐿 2 , and Δ 𝑀 in its self- and mutual-inductances, 𝐿 𝐴,1 , 𝐿 𝐴,2 , and 𝑀 𝐴 , respectively. We require 𝐿 𝐴,1 = 𝐿 𝐵,1 = 𝐿 𝐴,2 = 𝐿 𝐵,2 = 𝐿 and 𝑀 𝐴 = 𝑀𝐵 = 𝑀 to ensure a matched frequency response of the two branches. As a result, all of the inductors equivalent series resistances are also similar with 𝑅 𝐴,1 = 𝑅 𝐵,1 = 𝑅 𝐴,2 = 𝑅 𝐵,2 = 𝑅. It can be shown that under a sinusoidal drive signal with differential and common mode components 14 of magnitudes 𝑉𝑑 and 𝑉𝑐 , the voltage at each of the bridge outputs is 𝑉𝑑 𝑠(Δ 𝐿 2 + Δ 𝑀) · 2 𝑠(2𝐿 + 2𝑀) + 2𝑅 𝑠(2𝐿 + 2𝑀 + Δ 𝐿 2 + Δ 𝑀) + 2𝑅 + 𝑉𝑐 · , 𝑠(2𝐿 + 2𝑀) + 2𝑅 𝑉𝑜𝑢𝑡,𝑝 ≈ (2.22) 𝑉𝑑 −𝑠(Δ 𝐿 1 + Δ 𝑀) · 2 𝑠(2𝐿 + 2𝑀) + 2𝑅 (2.23) 𝑠(2𝐿 + 2𝑀 + Δ 𝐿 1 + Δ 𝑀) + 2𝑅 + 𝑉𝑐 · . 𝑠(2𝐿 + 2𝑀) + 2𝑅 It is important to note that unlike the approximation in [22], Δ 𝐿1 and Δ 𝐿2 are not assumed to be equal. The differential output voltage, 𝑉𝑜𝑢𝑡,𝑑𝑖 𝑓 𝑓 = 𝑉𝑜𝑢𝑡,𝑝 − 𝑉𝑜𝑢𝑡,𝑛 , can be approximated as 𝑉𝑜𝑢𝑡,𝑛 ≈ 𝑉𝑑 𝑠(Δ 𝐿 1 + Δ 𝐿 2 + 2Δ 𝑀) · 2 𝑠(2𝐿 + 2𝑀) + 2𝑅 𝑠(Δ 𝐿 2 − Δ 𝐿 1 ) . + 𝑉𝑐 · 𝑠(2𝐿 + 2𝑀) + 2𝑅 𝑉𝑜𝑢𝑡,𝑑𝑖 𝑓 𝑓 ≈ (2.24) If the bridge is excited with a differential input and drives a matched load, the 𝑉𝑐 dependent part of the output can be neglected, because it is multiplied by perturbation terms only. The inductor series resistance can be expressed in terms of the quality Magnetic Bead (not drawn to scale) Vin,p RA,1 LA,1 LB,1 RB,2 MB MA RB,1 LB,2 Core A Vin,p Vout,p Vin,n Vout,p Vout,n LA,2 RA,2 Vp , χ Vout,n Core B Vin,n (a) (b) Figure 2.6: A coupled inductive bridge. (a) Circuit schematics. Inductors with the same color share a core. (b) Physical implementation with a magnetic perturbation near one of the cores (not drawn to scale). 15 factor 𝑄 𝑒𝑞 = 𝜔(𝐿 + 𝑀)/𝑅 to give 𝑉𝑜𝑢𝑡,𝑑𝑖 𝑓 𝑓 ≈ 𝑉𝑑 Δ 𝐿 1 + Δ 𝐿 2 + 2Δ 𝑀 1 · · . 4 𝐿+𝑀 1 − 𝑗/𝑄 𝑒𝑞 (2.25) The result of (2.25) highlights three important characteristics of this topology. First, a perturbation of the coupled core produces a differential inductance shift equal to the shift that the same perturbation would have produced, had it been placed on the surface of a single inductor, composed of the series-connected core inductors 𝐿 𝑠𝑒𝑟 = 2(𝐿 + 𝑀). Hence, the amount of inductance shift as a function of beadparameters can be predicted using (2.13). Second, the denominator is composed of only half the series connected inductance. This leads to effectively twice the gain of a standard bridge. It is noteworthy that a similar voltage output could be achieved by using a four-inductor bridge with inductances of 0.5𝐿 𝑠𝑒𝑟 . However, such a structure will be about 1.5 times larger (excluding keep-out zones), would suffer from unwanted and unaccounted coupling effects, and would have a smaller effective sensing area compared to the coupled case. Third, since the sensed quantity is in quadrature with the series resistance, even moderately low values of 𝑄 𝑒𝑞 hardly affect the output. For example, in a core with a coupling factor 𝑀/𝐿 = 0.8 and 𝑄 𝐿 = 𝜔𝐿/𝑅 = 6, the differential output voltage degradation is less than 0.5%. Combining (2.14) and (2.25) gives the bridge transducer gain Δ 𝑉𝑑 𝐺𝑡 = 4 · 1 1 2 · · 2 𝜒𝑉𝑝 𝑢 𝐵0 · 106 𝐿 + 𝑀 1 − 𝑗/𝑄 𝑒𝑞 𝐼 (2.26) in units of [𝜇V/bead] where 𝑢 𝐵0 is the unperturbed magnetic energy density of the series connected core inductors and 𝜒 and 𝑉𝑝 are the susceptibility and volume of the bead, respectively. Input and output impedances Input and output impedances are important for the design of the bridge excitation and receiver circuits and are estimated by approximating the bridge outputs as opencircuits. The input impedance test circuit is shown in Fig. 2.7a. Due to symmetry, the test current 𝐼𝑡 is equally divided between the bridge branches so each inductor induces a voltage with magnitude 𝑠𝑀 𝐼𝑡 /2 in its coupled counterpart. The result is equivalent to four inductors sized (𝐿 + 𝑀), connected in series/parallel with an input impedance of 𝑍𝑖𝑛 ≈ 𝑠(𝐿 + 𝑀) + 𝑅. (2.27) 16 The output impedance test-current in Fig. 2.7b is equally divided between the excited-branch inductors, resulting zero current at the other branch. The mutual inductance has no effect and the differential output impedance is 𝑍 𝑜𝑢𝑡 ≈ 𝑠𝐿 + 𝑅 + 𝑅𝑠 (2.28) assuming an excitation source with an output impedance 𝑅𝑠 . The result in (2.28) is a worst-case scenario, since if the bridge input is tuned, then a parallel capacitor is added to it. At the tuning frequency, usually 𝑍 𝑐,𝑡𝑢𝑛𝑒 < 𝑅𝑠 and the output impedance becomes 𝑍 𝑜𝑢𝑡 ≈ 𝑠𝐿 + 𝑅 + 𝑍 𝑐,𝑡𝑢𝑛𝑒 . Noise considerations The coupled bridge is passive, so it only adds to the circuit the thermal noise associated with its inductor series-resistance. The other fundamental noise source is the excitation signal which propagates to the output and is not necessarily ideal. The noise associated with the source, 𝑒 𝑛,𝑆 , in Fig. 2.8a can be treated as correlated differential and common-mode components with identical amplitudes. These propagate to the output identically to (2.24), so the output noise due to each excitation source, It Vt It /2 It /2 RS RA,1 RB,2 RA,1 I=0 RB,2 LA,1 MB LB,2 LA,1 MB LB,1 MA LA,2 LB,1 MA LA,2 RA,2 RB,1 RS RB,1 (a) It /2 I=0 LB,2 It Vt RA,2 It /2 (b) Figure 2.7: Schematic circuits of the sensor’s (a) input impedance test circuit and (b) output impedance test circuit. 17 𝑒 𝑛,𝑜𝑢𝑡 |𝑆 , is p  < 𝑒 𝑛,𝑆 >2 ±𝑠(Δ 𝐿 1 + Δ 𝐿 2 + 2Δ 𝑀) < 𝑒 𝑛,𝑜𝑢𝑡 > |𝑆 ≈ 2 𝑠(2𝐿 + 2𝑀) + 2𝑅  𝑠(Δ 𝐿 2 − Δ 𝐿 1 ) , + 𝑠(2𝐿 + 2𝑀) + 2𝑅 (2.29) where ± is added to determine if we applied the source noise at the positive or negative input. The total noise at the output, due to two uncorrelated differential excitation sources, 𝑒 𝑛,𝑜𝑢𝑡 |𝑆,𝑡𝑜𝑡 , is then < 𝑒 𝑛,𝑜𝑢𝑡 >2 |𝑆,𝑡𝑜𝑡 ≈   2 2 2 2 (Δ 𝐿 1 + Δ 𝑀) + (Δ 𝐿 2 + Δ 𝑀) < 𝑒 𝑛,𝑆 > 𝜔 . | 𝑗𝜔(2𝐿 + 2𝑀) + 2𝑅| 2 (2.30) This noise is attenuated similarly to the excitation signal, and therefore is not of a major importance. The noise source associated with a single inductor series-resistance is shown in Fig. 2.8b. Since the unexcited bridge branch is grounded, its output voltage is 0V and the excited branch behaves like an impedance divider. Then, the output noise due to a single core inductor, 𝑒 𝑛,𝑜𝑢𝑡 | 𝐿 , is < 𝑒 𝑛,𝑜𝑢𝑡 >2 | 𝐿 ≈ ‹en,S›2 ∗ Vout,n RA,1 RB,2 LA,1 MA LB,2 < 𝑒 𝑛,𝐿 >2 . 4 ‹en,L›2 Vout,p ∗ Vout,n (2.31) RA,1 RB,2 LA,1 MA LB,2 Vout,p MB MB LB,1 LA,2 LB,1 LA,2 RB,1 RA,2 RB,1 RA,2 (a) (b) Figure 2.8: Schematic circuits of the sensor’s (a) excitation noise and (b) single inductor equivalent thermal noise. 18 Assuming that the thermal noises of all the inductors are uncorrelated, the total output noise due to the bridge inductors, 𝑒 𝑛,𝑜𝑢𝑡 | 𝐿,𝑡𝑜𝑡 , is < 𝑒 𝑛,𝑜𝑢𝑡 >2 | 𝐿,𝑡𝑜𝑡 ≈< 𝑒 𝑛,𝐿 >2 . (2.32) Integrated RF inductors are usually implemented in a thick metal layer where their equivalent series resistance is ∼0.5-10Ω [23]. This results in associated thermal √ noise densities up to ∼0.4𝑛𝑉/ 𝐻𝑧 [24]. Since the input-referred noise density of a √ typical bulk-CMOS amplifier is on the order of several 𝑛𝑉/ 𝐻𝑧, the thermal noise of the sensor is in most cases insignificant compared to the receiver’s input-referred noise. Parasitic effects In reality, the useful frequency of operation of an inductor is limited by its parasitic capacitance. Here, we lump the parasitic components into a few discrete devices as shown in Fig. 2.9. 𝐶 𝑝 and 𝐶𝑚 are the equivalent ground- and mutual-capacitances, respectively. Each inductor’s parasitic shunt capacitance is usually much smaller than those quantities and therefore neglected. For inductors with turns number 𝑁 > 1, 𝐶𝑚 pins are more naturally modeled between one inductor dot and the other non-dot ports, as shown in Fig. 2.9b. While more complex models could be used to describe the high frequency behavior, ours leads to an insightful result when embedded in the sensor cell with acceptable errors when compared to simulations as shown in 2.4. The complete model in Fig. 2.10a reduces to Fig. 2.10b, highlighting two independent resonance Cm Cp Cp M L L Cp Cp Cm (a) (b) Figure 2.9: A high frequency (a) coupled inductor model and (b) exemplary 2-turn layout. 19 frequencies: the input impedance is now frequency-dependent with resonance at 1 𝑓 𝑍,𝑖𝑛 ≈ (2.33) . p 2𝜋 (𝐿 + 𝑀)(𝐶 𝑝 + 2𝐶𝑚 ) Interestingly, the frequency-dependent excitation-to-output transfer function exhibits the same resonance frequency of 1 𝑓𝑜𝑢𝑡 ≈ 2𝜋 q (2.34) = 𝑓 𝑍,𝑖𝑛 . (𝐿+𝑀) 2 (2𝐶 𝑝 + 4𝐶𝑚 ) In reality, 𝑓 𝑍,𝑖𝑛 and 𝑓𝑜𝑢𝑡 slightly differ due to the distributed nature of the parasitic elements, but the approximation is very reasonable for design purposes. In this work, we define the self-resonance frequency as Δ (2.35) 𝑆𝑅𝐹 = 𝑓𝑜𝑢𝑡 , and require 𝑓𝑛𝑜𝑚𝑖𝑛𝑎𝑙  𝑆𝑅𝐹 so as to maintain the accuracy of our low-frequency model. Nevertheless, additional analysis could be performed to investigate the potential in tuning the sensor output to boost its voltage gain. 2.4 A Coupled Inductive Bridge - Proof-of-Concept Design Based on the analysis in 2.3, the five main parameters affecting a coupled bridge design are the maximum and flatness of the location-dependent transducer gain, the Cp Cp RA,1 Cp Cm LA,1 Cp RB,2 M1 M2 LB,2 2Cm+Cp Cm Cp Cp Cm (a) Cp Cp 2Cm +Cp Cm LB,1 RB,1 LA,2 RA,2 (b) Figure 2.10: A high frequency (a) coupled bridge model and (b) equivalent circuit. 20 Figure 2.11: Top: complex frequency response of two types of magnetic bead [9]. Bottom: change in magnitude of 𝜒 vs. frequency [15] for three bead types. self and mutual inductances which affect the excitation and receiver design, and the SRF which limits the frequency of operation. These must be tailored to fit the physical parameters of the sensed material. Choosing the frequency of operation Magnetic beads have been demonstrated to show rich frequency behavior [25], which can be exploited for various sensing schemes. This requires the use of a sensor with a suitable 𝑆𝑅𝐹. Fig. 2.11 overlays two previously measured datasets of the spectral properties of different beads [9][15] on top of the expected 𝑆𝑅𝐹 of our coupled sensor, for a different number of turns, 𝑁, and different diameters of the core inductors. The desired frequency of operation dictates the sensor size; for example, in order to measure the real part (or magnitude) of 𝜒 of iron-oxide nanoparticles up to 1GHz, we require 𝑆𝑅𝐹 > 5GHz. Hence, cores with 2-, 3-, or 21 0D[LPXP7UDQVGXFHU*DLQ 6HOIDQG0XWXDO,QGXFWDQFH $QDO\WLFDO 6LPXODWHG 1  1    1   1  /0>Q+@  1  1     1      ,QQHU'LDPHWHU> P@ D 7UDQVGXFHU*DLQ5DWLR $QDO\WLFDO 6LPXODWHG *DLQ5DWLR   1  1  1  1         ,QQHU'LDPHWHU> P@ F   65)>*+]@ 9%HDGPD[> 9@  1  /$QDO\WLFDO 0$QDO\WLFDO /6LPXODWHG    ,QQHU'LDPHWHU> P@ E 6HOI5HVRQDQFH)UHTXHQF\   $QDO\WLFDO 6LPXODWHG  1  1   1  1       ,QQHU'LDPHWHU> P@ G  Figure 2.12: Coupled bridge design parameters as a function of the inner core diameter and the number of the single-inductor turns. (a) maximum transducer gain, (b) self and mutual inductance, (c) gain ratio, (d) SRF. 4-turn inductors can be used with inner diameters smaller than 234𝜇m, 103𝜇m, or 30𝜇m, respectively. Fig. 2.12 shows how sensor performance metrics vary with the inner core diameter and 𝑁 when used to detect 4.5𝜇m Dynabead-Epoxy® beads. The bead susceptibility is assumed to be 𝜒=0.17 [26], but it is noteworthy that values up to 0.25 have also been reported [27][28]. These beads will be used throughout the paper as a baseline to verify our sensor performance. The transducer gain is calculated from (2.26) with 𝑢 𝐵0 either simulated or calculated from 𝐵0 , which can be approximated by (2.19). The maximum (Fig. 2.12a) and minimum transducer gains are defined on the sensor surface as shown in Appendix-2.4. Their quotient is the gain ratio in Fig. 2.12c which is a measure for the sensor’s gain flatness. The core inductances (Fig. 2.12b) and 𝑆𝑅𝐹 (Fig. 2.12d) are calculated using equations (2.36)-(2.39). 22 Figure 2.13: Comparison between the calculated and simulated transducer gain as a function of location above the sensor, (left) on 𝑥𝑧-plane, (right) on 𝑦𝑧-plane. Transducer gain and flatness. Fig. 2.14 shows the locations where the maximum and minimum transducer gains are defined. The location with the highest sensor gain is predicted to be near its traces. However, placing a bead there will affect the trace current and will violate the assumption in (2.3). Hence, we measure the maximum transducer gain at about twice the bead diameter inward from the traces–approximately 10𝜇m. The minimum transducer gain is defined on the sensor surface in the center of the core. Therefore, the ratio of the largest gain to the smallest gain is a measure for the gain flatness at a given height. The bead’s center is assumed to be 5.7𝜇m above the surface to account for its diameter of 4.5𝜇m, for the IC metal traces (3.4𝜇m thick), and for the chip oxide passivation (1.8𝜇m thick). Inductor model equations. The circuit parameters of Fig. 2.9a are determined as follows: each inductor inductance, 𝐿, is calculated using the modified wheeler equation [29] which for 23 Maximum gain location (0.5din-10, 0, 5.7)µm 10µm (0, 0, 5.7)µm Minimum gain location Figure 2.14: Bead location for the calculation of maximum and minimum gain parameters. octagonal inductors gives 𝑛2 𝑑 𝑎𝑣𝑔 , (2.36) 1 + 𝐾2 𝜌 where 𝐾1 = 2.25, 𝐾2 = 3.55 are shape constants for octagonal spiral, 𝑑 𝑎𝑣𝑔 = 0.5(𝑑 𝑜𝑢𝑡 − 𝑑𝑖𝑛 ) is the average diameter, and 𝜌 = (𝑑 𝑜𝑢𝑡 − 𝑑𝑖𝑛 )/(𝑑 𝑜𝑢𝑡 + 𝑑𝑖𝑛 ) is the fill factor. 𝑑 𝑜𝑢𝑡 , 𝑑𝑖𝑛 are the spiral inner- and outer-most diameters, respectively. 𝐿 𝑚𝑤 = 𝐾1 𝜇0 The ground capacitance, 𝐶 𝑝 , is calculated by considering the plate and fringe ground-capacitances of each inductor trace as in [30]:       𝑙𝑡𝑜𝑡 𝜖  𝑤 − 𝑡/2 2𝜋  𝐶𝑝 = + (2.37)  r    .   2  ℎ 2ℎ 2ℎ 2ℎ   log 1 + 𝑡 +  𝑡 𝑡 +2    Here 𝑙𝑡𝑜𝑡 is the total trace length, 𝜖 is the dielectric constant, and 𝑤, 𝑡, and ℎ, are the trace width, thickness, and height above substrate, respectively. The mutual capacitance, 𝐶𝑚 , is calculated from the total length of parallel coupled inductor traces, similarly to [31],   𝑡  0.222   𝑠  −1.34 𝑔𝑡𝑜𝑡 𝜖 𝑤 𝑡 𝑡 𝐶𝑚 = 0.03 + 0.83 − 0.07 , (2.38) 2 ℎ ℎ ℎ ℎ with the addition of 𝑠𝑡 , the trace spacing, and 𝑔𝑡𝑜𝑡 , the total length of the traces gap. Finally, the mutual inductance, 𝑀, is found from simply using (2.36) to find the inductance of the series-connected coupled inductors, and solving for 𝑀 in 𝐿 𝑠𝑒𝑟 = 24 ^z 87.2 80.9 120µm 74.5 90µm 68.1 60µm 61.8 30µm 55.4 49.1 42.7 36.3 30.0 23.6 17.2 ^x ^y (a) 120µm 90µm 60µm 30µm (c) ^z ^y ^x (b) Figure 2.15: Simulated magnetic field intensity with core inductors shorted in series. (a) On 𝑥𝑧-plane, (b) on 𝑦𝑧-plane, with (c) recorded values in 𝑑𝐵( 𝐴·𝑚 −1 ) (to increase contrast). 2(𝐿 + 𝑀): 𝑀= 𝐿 𝑠𝑒𝑟 − 𝐿. 2 (2.39) The series resistance does not play a major role in this sensor design, but can be calculated from [23] if needed. Magnetic field profile One implication of (2.25) and (2.26) is that the sensor gain is proportional to the energy density profile of the series-connected core inductors. Fig. 2.13 draws comparison between the transducer gain that was calculated from the magnetic field predicted in (2.19) and the gain that was derived from the simulated fields of a similarly-sized sensor core. One comparison was done using the field values on the 𝑥𝑧-plane (Fig. 2.15a) at several heights above the sensor surface. A second 25 comparison was done on the 𝑦𝑧-plane (Fig. 2.15b) to illustrate the difference in results due to the core leads and trace cross-overs, which are not included in the analytical model. Core sizing For a prototype design, we chose a 2-turn, 200𝜇m inner-diameter sensor core. It has 𝑆𝑅𝐹 ≈6GHz with maximum gain and gain-ratio of 2𝜇V/bead and 4, respectively. The self- and mutual-inductances are 𝐿 ≈1.7nH and 𝑀 ≈1.3nH. This choice of parameters allows to easily sense a single 4.5𝜇m bead at the sensor surface as well as to conveniently tune its input at the low-GHz range. To finalize the design, the chosen core was simulated with a commercial 3D-EM software [32]. A comparison between the gain-profile from calculated and simulated magnetic energy density is shown in Fig. 2.13, demonstrating the accuracy of the model presented in 2.1. The only differences are on the 𝑦𝑧-plane near the leads and trace cross-overs which are not considered in the analytical calculation as discussed in Appendix 2.4. Excitation and receiver A sensor cell based on the core dimensions chosen in 2.4 was integrated with excitation and receiver circuitry in a 65nm bulk CMOS process (Fig. 2.16). The input driver stage is designed to have sufficient gain such that the excitation voltage is amplitude-limited at 1.6V differential peak-to-peak using a 1V supply. In addition, it includes a six-capacitor bank for frequency tuning. The receiver includes a summing amplifier for the offset-cancellation (OC) scheme detailed in 2.4. Both receiver and OC paths were designed with CMRR>60dB to decrease common mode offsets. Their simulated gains are 24dB and 19dB, respectively, to buffer and sufficiently amplify the bridge output. The receiver’s simulated input-referred noise is lower √ than 10nV/ 𝐻𝑧, theoretically allowing a measurement of 500nV at the sensor output with an SNR=10dB at a 250Hz bandwidth or, equivalently, with a detection time of ∼3ms[33]–fast enough for cell-sorting applications [9]. Additional peripheral circuitry include an RF-to-DC amplitude detector for driver swing estimation and four thermometers for temperature gradient monitoring. Offset cancellation Our bridge sensor features matching characteristics which cancel most of its output offsets. Despite that, small residual offsets might result from branch mismatch, signal feedthrough, and temperature gradients. These can be canceled by subtracting 26 VDDin OC Replica Out Vin,p =Vd /2 RA,1 RB,2 LA,1 LB,2 M2 M1 LB,1 RB,1 Ctune ICin,n VDDout ICout,n ICout,p Conditioned OC In Vout,p Vout,n LA,2 RA,2 ICin,p Vin,n =-Vd /2 Sensor Cores Input Driver Receiver With OC Figure 2.16: Simplified schematics of the fabricated IC. vin Sensor cell vout vrec Receiver Amp a φ Null Amp. Variable Gain Variable Phase Summing Amplifier vsum vOC Figure 2.17: General structure of offset cancellation scheme. a phase-shifted and attenuated replica of the excitation voltage from the received signal. Offset Cancellation (OC) can be done at the frequency of operation (RF) or in a down-converted signal. While high-resolution OC at RF is more difficult to implement, it relaxes the demands on the receiver input dynamic range. Fig. 2.17 shows a general OC scheme for the fundamental tone of harmonic signal with an amplitude 𝐴 and a radial frequency 𝜔 𝑣 𝑟𝑒𝑐 = 𝐴 · cos 𝜔𝑡. (2.40) The subtraction of a phase shifted and attenuated replica of the excitation signal 𝑣 𝑂𝐶 = 𝐴𝑎 · cos (𝜔𝑡 + 𝜑) (2.41) 27 from 𝑣 𝑟𝑒𝑐 results in an output, 𝑣 𝑠𝑢𝑚 , with a frequency 𝜔 and an amplitude of q 𝐴𝑠𝑢𝑚 = 𝐴 𝑎 2 − 2𝑎 cos 𝜑 + 1, (2.42) which should be nulled in order to cancel offsets prior to taking actual measurements. Clearly, the relative phase shift, 𝜑, required to perfectly null the output is, to the first order, independent of the amplitude scaling factor 𝑎. Hence, an iterative binary search algorithm can be utilized to calibrate the sensor with a logarithmic complexity. If 𝑎 and 𝜑 in (2.42) are both set digitally by 𝑁- and 𝑀-bit DACs, respectively, then the worst-case attainable OC is s  2   𝐴𝑠𝑢𝑚 1 𝜋 1 = 1 − 𝑁 − 2 1 − 𝑁 cos 𝑀 + 1. (2.43) 𝐴 2 2 2 One subtlety in (2.43) is that the amplitude DAC is assumed to only cover the range up to the (unknown) output offset. If the replica OC signal is much larger than the offset in the received signal, additional bits are required for initial adjustments– approximately 3.5 bits for every 20dB of initial output uncertainty. Fig. 2.18 shows the achievable OC as a function of the number of phase and amplitude control bits. Our sensor IC is designed for evaluation purposes and does not include downconversion circuitry. Therefore, OC currently is done only at RF. For the same reason, offset signal conditioning is implemented off-chip with 12- and 16-bit phase and amplitude controls, respectively. :RUVW&DVH2&IRU1%LW$PSOLWXGHDQG0%LW3KDVH'$& 1  $WWHQXDWLRQIRU1%LW$PS'$& 1  1  1  1  1  1  2&FDQFHOODWLRQ>G%@              3KDVH'$&UHVXOXWLRQ>0%LWV@   Figure 2.18: Attainable offset cancellation as a function of amplitude and phase control number of DAC bits. 28 1000μm RF-DC Output & OC m Signal Input Source Driver OC out Sens. cell 200µm Sens Offset Cancellation (a) Signal In 330µm 1500μm Temp x4 Sensor IC Signal Detection System Monitoring Signal out OC in (b) Figure 2.19: Top level view: (a) simplified measurement system schematics and (b) the chip die photo. Sensor system characterization The IC die photo and system schematics are shown in Fig. 2.19. No additional processing is done besides a back-lapping of the chip to a standard thickness of 300𝜇m. For evaluation purposes, the output amplitude is recorded with a spectrum analyzer. Prior to detecting magnetic beads, additional performance characterization was carried out. Input swing and receiver gain estimation The sensor transducer gain (in 𝜇V/bead) is proportional to the bridge excitation swing (2.26), which is not directly accessible. To estimate it, we have integrated an RF-to-DC detector at the bridge input. The detector output was measured with variable input power (Fig. 2.20a) and at different tuning frequencies (Fig. 2.20b). Its close match with the simulation results leads to an estimated differential input swing of 1.6V peak-to-peak. In addition, it is necessary to know the bridge output voltage. However, its output is buffered by the receiver signal path, which is not directly measurable. Here, we use the OC path as a surrogate for the receiver path gain estimate. For that purpose, both paths are designed as cascades of identical amplifiers–six for the receiver and four for the OC. The OC path gain was measured (Fig. 2.21) and compared against simulation. The good agreement between the two results leads to an estimate of a 5dB difference between the receiver and OC path gains. The input driver and receiver consume 8.7mW and 11mW (including the OC amplifiers) at 100% duty cycle, respectively. 29 RF-DC power sensor Vg Vg Vrf,p Vrf,n Vdc Figure 2.20: Measurement vs. simulation of (a) input power saturation, and of (b) input matching. Figure 2.21: Comparison between the simulated and measured OC path gain to the simulated receiver gain. 30 Spatial transducer gain profile Next, the spatial transducer gain profile of the inductively-coupled sensor was characterized (Fig. 2.22). This was done with a solid 15𝜇m-diameter iron oxide bead which is small enough to obtain localization information, but generates a large enough signal such that offset errors are negligible. Gain reduction vs. height was measured at several sites above the sensor surface and compared to simulations (Fig. 2.23). The measured attenuation rate is about 0.23dB/𝜇m and agrees well with the simulated results of 0.27dB/𝜇m, especially given the uncertainty in height measurement and location on the sensor surface. These results are important for cytometry applications, where a microfluidic channel can be tens of micrometers high [9] with implications on the choice of the sensor inductor size; smaller inductances may be required in order to increase the sensitivity, as shown in (2.26). The gain is lower at the sensor leads (Fig. 2.23-right) and at its center, where the magnetic field intensity is lower. This is a common feature of all inductor-based sensors. If necessary, the optimization proposed in (2.12) or the method discussed in [34] can be adopted to achieve a horizontally uniform gain profile. X1 𝒛 Y1 X2 Y2 Y3,X3 X4 Y4 Y5 X5 𝒚 𝒙 Figure 2.22: Probe locations for gain profile characterization. Magnetic particle detection Finally, the sensor performance was quantified by measuring several groups of 4.5𝜇m Dynabead-Epoxy® magnetic beads bonded to non-magnetic probes. Measurements are taken in dry media as shown in Fig. 2.24. Each measurement includes an OC calibration followed by 30 minutes of application/removal of the probe using a micro-positioner. OC reduces the measured offset from 0.4mV to less than 3𝜇V at the output of the sensor cell within less than 20 steps. Even though small temperature fluctuations, on the order of single degrees, were observed during the 31 ;=3ODQH6LP $WWHQXDWLRQ>G%@   ;=3ODQH0HDV                 X1 P X2 P X3 P    X1 P X2 P X3 P   X4 P X5 P        +HLJKW$ERYH6XUIDFH> P@ <=3ODQH0HDV  Y1 P Y2 P Y3 P Y4 P Y5 P   Figure 2.23: Gain profile degradation vs. height on 𝑦𝑧-plane (right) and 𝑥𝑧-plane (middle) compared to simulation prediction (left). measurements, no in-depth investigation of the temperature-dependent behavior was carried at this time. All measurements were done at 770MHz to minimize spectral interferences from cellular bands and other laboratory equipment. The output signal is currently recorded using an additional off-chip receiver in order to verify the sensor cell performance, with the intention to integrate an on-chip baseband in the future. Fig. 2.25 shows a typical response of our coupled bridge sensor to several discrete quantities of magnetic beads. These are raw measurements that were averaged using a 16-point sliding-window for presentation purposes. The mean (dotted lines) and ±1𝜎 standard deviation (grey) are overlaid on the output readings, demonstrating a clear distinction between "high" and "low" output values over the whole measurement interval. These results show a stable, continuous detection over significantly longer time periods compared to previously reported similar works. The measurements of Fig. 2.25 were repeated several times at several locations on the sensor surface and demonstrated similar, continuously stable responses over periods at least half an hour long. The average sensor output voltage as a function of the number of applied beads is summarized in Fig. 2.26. Qualitatively, these results match the measured gain profile of Fig. 2.23. Quantitatively, the measured transducer gain is up to 1.15𝜇V/bead at the sensor edge and 0.38𝜇V/bead in its center, compared to the predicted values of 2.1𝜇V/bead 32 To signal detection Phase/Amp. conditioning Signal in Micro-positioner arm Non-magnetic probe Probe Air Bead(s) 3.5μm 6.9μm Sensing Area Cross-Section Oxide Intrinsic Silicon Inductor Trace Figure 2.24: Measurement system, including OC circuitry. and 0.46𝜇V/bead, respectively. The lower measured gain can be attributed to three factors. First, beads near a sensor trace might affect the current distribution in it, violating the assumption in (2.3). Second, the transducer gain was already shown to decrease by about 0.25dB/𝜇m with height (Fig. 2.23) above it, so if the beads are not flush at the chip surface, significant loss is expected. Finally, measurements are done at RF, where | 𝜒| may be lower than its DC values (Fig. 2.11). Considering these facts, the measurements agree well with our predictions. The good agreement both verifies that the coupled bridge works as intended and supports the theoretical background that was developed in 2.1. 2.5 Conclusions This work presents a systematic approach to the design of magnetic susceptibility sensors. A novel, all-inductor, fully symmetrical bridge sensor is demonstrated as a proof-of-concept of the design approach. By fabricating the bridge sensor along with integrated excitation and receiver circuitry, as well as carefully characterizing its performance and employing an efficient offset cancellation scheme, we show how our physical model and sensory system can be designed to the desired specifications. Though only a prototype, the coupled bridge was demonstrated to reliably detect 4.5𝜇m magnetic beads with significantly improved long-term stability in comparison to state-of-the-art, as shown in Table 2.1. Sensor output voltage [µV] 33 10 8 6 4 2 0 10 8 6 4 2 0 0 10 8 6 4 2 0 5 10 15 20 25 Blank (control) 30 5 0 10 8 6 4 2 0 ±𝛔 0 ±𝛔 10 15 20 3 Beads 25 30 5 10 15 20 1 Bead 25 30 10 15 20 7 Beads 25 30 ±𝛔 0 Time [minutes] 5 Figure 2.25: Exemplary system response to different amounts of 4.5𝜇m iron-oxide beads. Output voltage [µV] 10 Top Left Bottom Right Middle 8 6 4 2 0 0 1 2 3 4 5 6 Number of probed beads 7 8 Figure 2.26: Sensor cell response for 4.5𝜇m beads at various locations on the core surface. 34 Table 2.1: Comparison table ISSCC 09’[5] ISSCC 14’[8] JSSC 17’[9] Sensor Type LC tank Transformer Transformer Target App. Immunoassay Cytometry Cytometry 1𝜇m 4.5𝜇m 4.5𝜇m 4.5𝜇m 90 seconds 3 seconds 20 seconds 30 minutes No Dummy Tank No N/A 15x15𝜇m 30x30𝜇m 200x200𝜇m Min. Bead Size (iron-oxide) Long Term Stability Additional Inductors Effective Sensing Area This work Bridge Immunoassay/ Cytometry 35 Chapter 3 CALTECH’S SPACE SOLAR POWER PROJECT 1 3.1 Introduction The idea to collect solar power in space and send it down to earth is over half a century old. It was presented in both fiction [35] and technical [36] literature, and is appealing because it overcomes major issues of terrestrial photovoltaic conversion. Space-based solar power is not affected by weather, avoids atmospheric attenuation and reflection, and is potentially continuously available throughout the day. Physically delivering the collected power with cables or elevators is not currently feasible due to the associated distance and assembly weight. Hence, the vast majority of published work aims to convert the solar power and send it down to earth in the form of an electromagnetic beam. Though this method is presumably inefficient due to the energy conversion and focusing losses, its practical advantages in terms of cost, mass, and manufacturability seem to overcome the drawbacks. Additionally, an EM beam may be electrically steered to provide dynamic power delivery and splitting, which makes the concept very appealing for commercial, emergency, and defense uses. Such a radiating array launched into space can presumably include EM receivers to perform remote sensing and measurement missions to further increase its functionality and therefore its economic and scientific value. Surprisingly, the main challenge is not solar-to-EM power conversion efficiency per se. A quick look at Glaser’s original proposal in Fig. 3.1 for a power-converting satellite highlights the main difficulties with this design. The solar power density is given at about 1.36kW/m2 in space and the radiated beam width of an antenna is inversely proportional to both its aperture size and frequency of operation. Therefore, transmitting and focusing a reasonable amount of power from a single power satellite require a large solar panel and a sizable aperture antenna on the same structure. Operating at high frequencies can only ease the problem to a limit, above which the loss associated with the conductors and active components is unacceptable. It will be quantitatively shown that with the current cost of launching mass into space, previously proposed solar power architecture make little economic sense in terms of the expected income versus the cost of space segment fabrication/ deployment. 1 This work was done in collaboration with Dr. F. Bohn, Dr. B. Abiri, Dr. M.R. Hashemi, and A. Fikes. 36 The system’s design challenges are therefore to maximize the specific power in W/kg radiated by the array, to improve its longevity, and to expand its functional capabilities. Caltech has identified solar space power research as an important frontier in science and sustainability. A collaboration of researchers in the field of electronics, photovoltaics, and lightweight space structures has been working since 2015 on the development of novel architectures, structures, and circuits to enable feasible space-based power transfer. The main approach is to take advantage of technology advances and custom designed integrated circuits to significantly reduce space-based radiator weight and therefore launch cost, as will be shown in the following chapters. During my time at Caltech, I had the privilege to be part of the RF electronics team in this collaboration. Our main achievement to date is a first demonstration of a lightweight, modular, and fully integrated solar-to-RF power conversion unit (tile) with an exceptional power-to-mass ratio meant to be the basic building block of a future space power delivery system. The next sections will describe the space-solar power system with an emphasis on the electrical functionality. I will further detail my contributions to the project from the aspects of timing synchronization, system level integration, and thermal reliability. Figure 3.1: Glaser’s original patent drawing of a solar power satellite. 37 3.2 System Overview Cost Perspective The main challenge with space-based power delivery is to design an economically viable system. Even though some benefits of space-based power like dynamic beam steering are hard to quantify and monetize, an approximate estimate of space power economics is crucial to evaluate the system viability. This chapter will derive a rough estimate of space-based power levelized cost of electricity (LCOE), compare it to current energy costs, and draw system-level conclusions. Some of the assumptions are technology-dependent or estimated magnitudes and are not fundamental limits to system performance. Nevertheless, this exercise is important to understand the design-space and the variables that determine this concept’s feasibility. The discussion starts with the estimated energy costs in selected countries and in US expeditionary operations, shown in table 3.1 and in Fig. 3.2. While the prices slightly change between different surveyors [37][38], these approximate values are sufficient for the discussion that will follow. Table 3.1: Average worldwide prices for electrical power∗ Country Egypt China South Africa United States∗∗ Australia Japan Germany ∗ Data from [37] ∗∗ Data from [39] US Cents/kW·h 4 8 11 7.7 - 19.36 [Hawaii - 29.18] 22 28 35 Year Updated 2019 2019 2019 2018 2019 2019 2019 Clearly, the cost of energy in remote operations is orders of magnitude higher than in well established populated areas. For this reason, the solar space power concept might be initially more appealing to defense operations, disaster response, or rural areas. Derivation of the space segment contribution to SSP LCOE 2 The expected contribution of the space segment to the LCOE of space-based power is a function of the deployment cost of the space segment 𝐶𝑠𝑠 , the received power 2 Based on data and derivation from [41] and [40], with newly developed results and insights. 38 Figure 3.2: Cost of expeditionary power. Both JP8 cost and the JP8 cost of transport to destination affect total cost in operation [40]. on grid 𝑃𝑔 , and the total illumination time expressed as 𝑇𝑖𝑙 [ℎ/𝑦𝑟] · 𝑇 [𝑦𝑟 𝑠] 𝐿𝐶𝑂𝐸 𝑠𝑠 = 𝐶𝑠𝑠 [$/𝑘𝑊 · ℎ]. 𝑃𝑔𝑇𝑖𝑙 𝑇 (3.1) Received power The received power on ground can be found from the modified Friis formula [42]  𝑓 𝑃𝑔 = 𝑐·𝑟 2 𝑃 𝐷𝐶 𝜂𝑡 𝐴𝑡 𝐴𝑟 𝜂𝑟 , (3.2) where 𝑓 is the frequency of operation, 𝑐 is the speed of light, 𝑟 is the distance between transmitter and receiver, and 𝑃 𝐷𝐶 is the DC power supplied by the photovoltaic cell. This equation can be further expanded as follows: the transmitted power 𝑃 𝐷𝐶 𝜂𝑡 can be re-written as 𝑃 𝐷𝐶 𝜂𝑡 = 𝐼 𝐴𝑀0 𝐴𝑃𝑉 𝜂 𝑠𝑠 , (3.3) where 𝐼 𝐴𝑀0 is the sun power density in space of 1.36kW/m2 , 𝐴𝑃𝑉 is the photovoltaic receiver area, and 𝜂 𝑠𝑠 is the total space segment conversion efficiency from solar to transmitted RF power. One special assumption that we will use throughout this calculation is that the stringent weight requirements effectively force a uni-body carrier for both the PV and RF modules of the space craft. Then, the most efficient 39 utilization of area is with 𝐴𝑃𝑉 = 𝐴𝑡 and the received power can be re-written as  𝑓 𝑃𝑔 = 𝑐·𝑟 2 𝐼 𝐴𝑀0 𝐴𝑡 2 𝐴𝑟 𝜂 𝑠𝑠 𝜂𝑟 . (3.4) The efficiencies associated with the space segment and ground power conversion can be further expanded to 𝜂 𝑠𝑠 = 𝜂 𝑃𝑉 · 𝜂 𝐷𝐶 𝑅𝐹 · 𝜂𝑇𝑥 , (3.5) in which – 𝜂 𝑃𝑉 = Photovoltaics to DC conversion efficiency – 𝜂 𝐷𝐶 𝑅𝐹 = DC to RF conversion efficiency – 𝜂𝑇𝑥 = Transmitting antenna efficiency, and 𝜂𝑟 = 𝜂 𝑑𝑖 𝑓 𝑓 · 𝜂 𝑅𝐹 𝐷𝐶 · 𝜂 𝐷𝐶 𝐴𝐶 , (3.6) with – 𝜂 𝑑𝑖 𝑓 𝑓 = Main lobe power (diffraction efficiency) – 𝜂 𝑅𝐹 𝐷𝐶 = RF to DC conversion efficiency including rectenna – 𝜂 𝐷𝐶 𝐴𝐶 = DC to grid AC conversion efficiency. Lastly, the ground receiver rectenna array is designed to fill the projected area of the main lobe from the SSP spacecraft(s). Depending on the orbit and the size of the transmitting aperture, the receiving rectennas can be either in the near or far field. Assuming circular apertures, the receiver aperture size 𝐴𝑟 can be written as 2 𝐴𝑟 = (𝑟𝜃) = 𝑟 2  2   𝑟𝐴2𝑡 + 𝑓 𝑐2 𝐴  𝑐2   𝑓 2𝐴  𝑡 𝑟 < 2𝐴𝑡 𝑓 /𝑐 𝑡 (3.7) . 𝑟 > 2𝐴𝑡 𝑓 /𝑐 Substituting (3.4) into (3.7) gives     2  𝑓 𝐴 𝑡  + 1 𝐼 𝐴𝑀0 𝐴𝑡 𝜂 𝑠𝑠 𝜂𝑟  𝑐𝑟  𝑃𝑔 =    𝐼 𝐴𝑀0 𝐴𝑡 𝜂 𝑠𝑠 𝜂𝑟  𝑟 < 2𝐴𝑡 𝑓 /𝑐 . 𝑟 > 2𝐴𝑡 𝑓 /𝑐 (3.8) 40 Orbital considerations One of the primary challenges with space-based solar power is the design and maintenance of a satellite constellation in formation. In the past decade, substantial amount of research has been done on the guidance, navigation, and control of formation flying satellites [43][44]. Formation flight has also been demonstrated in space by missions such as GRACE [45], GRAIL [46], and PRISMA [47]. The detailed design of the formation flying constellation along with the associated sensing and actuation requirements is currently being pursued and will be presented at a later date. A critical decision in the orbital design of the space solar constellation is the choice of the orbit altitude. From a launch cost perspective, low Earth orbits (LEO) are easier to get to and place less stringent requirements on the beamwidth of the antenna array. But a LEO constellation would not be able to generate power 40% of the time on account of being eclipsed by the Earth. While the constellation could be placed in a terminator orbit (polar sun-synchronous 6am-6pm), it leads to a highly inefficient orientation for RF transmission. The LEO constellation would also require a network of ground-based receivers on Earth to continuously relay power from the space-based array. Moreover, in low Earth orbit, one must deal with orbital perturbations due to atmospheric drag, Earth oblateness (J2), and solar radiation pressure, further complicating the guidance, navigation, and control problem. On the other hand, a constellation in GEO can radiate all its power to a single ground-based receiver. The spacecraft is always in view of the sun, except for a few days of the year close to the equinoxes when the Earth eclipses the sun for up to an hour each day. While the electronics in GEO must survive a harsher radiation environment than LEO, maintaining a constellation in formation flight is relatively easier since we only have orbital perturbations from solar radiation pressure. Keeping these factors in mind, the point design presented in this paper assumes that the constellation is in GEO. Cost of space array deployment The number of spacecrafts 𝑁 𝑆𝑉 that are needed to generate a total power of 𝑃𝑔 is   𝐴𝑡 (3.9) 𝑁 𝑆𝑉 = 𝐴𝑆𝑉 41 with 𝐴𝑆𝑉 being a single spacecraft area. Substituting (3.8) into (3.9) yields        𝑃  𝑔       𝑓 𝐴  2    𝑁 𝑆𝑉 =  𝑐𝑟 𝑡 +1 𝐼 𝐴𝑀 0 𝐴𝑆𝑉 𝜂𝑠𝑠 𝜂𝑟     l m   𝑝𝑔   𝐼 𝐴 𝜂 𝜂  𝐴𝑀 0 𝑆𝑉 𝑠𝑠 𝑟 𝑟 < 2𝐴𝑡 𝑓 /𝑐 . (3.10) 𝑟 > 2𝐴𝑡 𝑓 /𝑐 The ceiling operation accounts for the integer amount of spacecrafts in an array. There are a limited number of launchers at present, capable of putting large payloads into GEO. We characterize a given launch system’s capability by 𝑀𝐺𝐸𝑂 , the mass that the launcher can place into GEO, and 𝜅, a de-rating factor for the launcher, acknowledging that some reserve mass is needed to accommodate uncertainty in the mass of the space vehicles and supporting structure for the space vehicles on the launcher [48]. Given 𝜅 and 𝑀𝐺𝐸𝑂 , and the mass of the space vehicle, we can compute the number of space vehicles with mass 𝑚 𝑆𝑉 that a given launcher can place into GEO, 𝑛𝑆𝑉   𝜅𝑀𝐺𝐸𝑂 0 < 𝜅 < 1. (3.11) 𝑛𝑆𝑉 = 𝑚 𝑆𝑉 The number of launches needed to place all spacecrafts in GEO, assuming integer number of vehicles can fit in a launcher, is then   𝑁 𝑆𝑉 . (3.12) 𝑁𝐿 = 𝑛𝑆𝑉 The specific power 𝑆, radiated by each spacecraft in the array, can be defined as 𝑆= 𝐼 𝐴𝑀0 𝐴𝑆𝑉 𝜂 𝑠𝑠 . 𝑚 𝑆𝑉 (3.13) Substituting (3.13) into (3.10) expresses 𝑁 𝑆𝑉 in terms of the SSP system specific power independently from its mass. Since 𝑆 contains all the design-space variables of the Tx/Rx performance and is decoupled from the launch cost parameters, it should be the optimization objective for the space segment design. With knowledge of 𝑁 𝑆𝑉 and 𝑁 𝐿 , we begin to see how the system cost, and ultimately the levelized cost of electricity scale with 𝑃𝑔 and 𝑚 𝑆𝑉 . Fig. 3.3 shows the trends for the number of space vehicles and launches as a function of power to the grid based on a Falcon 9 Heavy launcher capable of placing 3,000 kg (3 MT) to GEO. Since both 𝑁 𝑆𝑉 and 𝑁 𝐿 are linearly dependent on 𝑃𝑔 , the space vehicle’s mass and area determine the slopes of the graphs of both quantities as functions of 𝑃𝑔 . Based on these relationships, we can estimate the cost of the space portion of an SSP system. To get a reasonable estimate for the space vehicle cost (payload, spacecraft, 42 Figure 3.3: 𝑁 𝑆𝑉 and 𝑁 𝐿 are linearly dependent on 𝑃𝑔 . The slopes of the curves depend on the specifics of the space vehicle [41]. integration, testing, etc.), CSV, we employ a rule of thumb that space vehicles cost between $90,000-$250,000/kg on-orbit. The variation has to do with the space vehicle complexity, mission requirements, operational lifetime, etc. Another way of looking at the cost spread is the difference between building satellites for Class A, B, C, or D missions [49]. Class A is an operational mission with lowest possible risk, and is usually the most costly of the four classes. We assume that the SSP space vehicles are similar to Class A missions and use $200,000/kg as a cost scaling figure. The launchers’ cost, 𝐶 𝐿 , is between $90M for a Falcon 9 Heavy to $200M for an Ariane 6. A reasonable upper limit for the space portion cost is 𝐶𝑆𝑆 = 𝐶𝑆𝑉,𝑘𝑔 · 𝑚 𝑆𝑉 · 𝑁 𝑆𝑉 + 𝐶 𝐿 · 𝑁 𝐿 . (3.14) It is noteworthy that (3.15) ignores any cost decrease due to learning curves to produce the satellites and the launchers. Learning curves acknowledge the increase in efficiency of production of an item as the number of items produced is increased [50]. The equation also assumes that every launch is successful and that every satellite works to specification once on orbit. These are optimistic assumptions and therefore (3.15) provides a lower upper bound on cost for the space segment. 43 Table 3.2: Estimated values for 𝐿𝐶𝑂𝐸 𝑆𝑆 calculation Variable 𝐼 𝐴𝑀0 𝑟 𝐴𝑆𝐶 𝑓 𝜂 𝑃𝑉 𝜂 𝐷𝐶 𝑅𝐹 𝜂𝑇𝑥 𝜂 𝑑𝑖 𝑓 𝑓 𝜂 𝑅𝐹 𝐷𝐶 𝜂 𝐷𝐶 𝐴𝐶 𝑃𝑔 𝐶𝑆𝑉,𝑘𝑔 𝑀𝐺𝐸𝑂 𝜅 𝐶𝐿 𝑇𝑖𝑙 𝑇 Value Details 1366 W/m2 40,000 km 3600 m2 10 GHz 0.25 0.5 0.96 0.84 0.82 0.9 50 MW 200 $K 3000 kg 0.97 90 $M 8684 hr/yr 20 years GEO height plus steering angle Based on structural design See "Selection of operating freq." below Off-the-shelf best in class PV efficiency CMOS IC PA efficiency around X-band High performance RF antenna loss at X-band Center lobe power for circular array Rectenna efficiency AC grid conversion efficiency Power to grid design target Estimated above Falcon 9 Heavy 3% of 𝑀𝐺𝐸𝑂 Falcon 9 Heavy 24 ℎ𝑟/𝑑𝑎𝑦 illumination except eclipses Goal mission duration Expected mission time Assuming that the satellites operate at GEO, then they can produce energy 365 days a year, 24 hours a day except for twice a year during equinoxes. The total yearly eclipse time is approximately 80 hrs (the maximum daily eclipse time is less than 1 hour 10 minutes), so the total solar illumination time 𝑇𝑖𝑙 is about 8,684 ℎ/𝑦𝑟. Quantifying the space segment contribution to the LCOE With all parameters of (3.1) defined, we can now plot the space segment contribution to the LCOE as a function of launch cost and specific power. Table 3.2 shows the design goals and estimated values of 𝐿𝐶𝑂𝐸 𝑆𝑆 equation variables. Fig. 3.4 and Table 3.3 show the contribution of the space segment to SSP - 𝐿𝐶𝑂𝐸 𝑆𝑆 . Three specific data points are highlighted. The first is a fully integrated PV/RF unit cells which was built with available technologies and demonstrated as part of Caltech’s SSP program. It measures 165 mm × 100 mm and weights 16.2 g, which scales to a PV/RF weight of 3530 kg for a 60 m × 60 m spacecraft. The 44 Figure 3.4: Space segment contribution to LCOE vs. spacecraft specific power. Table 3.3: Estimated values for 𝐿𝐶𝑂𝐸 𝑆𝑆 calculation Quantity 𝑚 𝑆𝑉 [kg] 𝑆 [W/kg] 𝑁 𝑆𝑉 𝑁𝐿 Spacecraft Cost [$B] Launch Cost [$B] 𝐿𝐶𝑂𝐸 𝑆𝑆 [$/kWh] Demonstrated 3605 163 137 170 98.8 15.3 13.1 Goal 651 906 137 35 17.8 3.2 2.4 Competitive 107 5515 137 6 2.9 0.5 0.4 second is a mid-term design goal with ambitious but realistic build materials, of 1.6 g for a 100 mm × 100 mm unit cell. This translates to an RF/PV weight of 576 kg for a 60 m × 60 m spacecraft. An approximate wight of about 75 kg is assumed for the supporting deployment components: hubs, longerons, booms, etc. The last data point is a calculation of the required array specific power and mass to achieve 𝐿𝐶𝑂𝐸 𝑆𝑆 = 0.4. This amount of specific power will position an SSP system LCOE in the ≈ $0.5 range - competitive relative to current energy costs in developed European countries, for example. In contrast, Fig. 3.5 and Table 3.4 calculate what should be the reduction in spacecraft build and launch costs, to make our demonstrated and goal designs competitive in terms of raw LCOE. This is done by introducing a cost reduction 45 (VWLPDWHG/&2(FRQWULEXWLRQYVUHGXFWLRQLQVSDFHFUDIWDQGODXQFKFRVW  6SDFHVHJPHQW/&2(>N:K@ 'HPRQVWUDWHG     *RDO           6SDFHFUDIWEXLOGDQGODXQFKFRVWUHGXFWLRQ  Figure 3.5: Space segment contribution to LCOE vs. reduction in the cost of build and launch of an SSP spacecraft. Table 3.4: Estimated values for 𝐿𝐶𝑂𝐸 𝑆𝑆 calculation Quantity 𝑚 𝑆𝑉 [kg] required cost reduction∗ Total Spacecraft Cost [$B] Demonstrated 3605 0.03 2.96 Total Launch Cost [$B] 0.46 Spacecraft Build Cost [$K/kg] 6.0 Single Launch Cost [$M/Launch] 2.7 Spacecraft Build+launch Cost [$K/kg] 6.93 ∗ Assumed proportional reduction in build and launch costs Goal 651 0.166 2.96 0.52 33.2 14.94 39.06 factor, 𝛼 such that 𝐶𝑆𝑆 = 𝛼(𝐶𝑆𝑉,𝑘𝑔 · 𝑚 𝑆𝑉 · 𝑁 𝑆𝑉 + 𝐶 𝐿 · 𝑁 𝐿 ). (3.15) Note that without additional information, we assume a proportional reduction in both build and launch costs over time. 46 Conclusions The calculation above is a simplified cost estimate. Several other important factors that might affect the final system LCOE are: RF phased array’s array coefficient, angular efficiency of the PV cells, receiving and transmitting energy when earth is between the sun and the array, financing/loan issues of such a high cost project, and more. It does, however, provide very useful information. It is clear that the system viability is highly dependent on its specific power and that with current technologies, with the current costs of similar extraterrestrial missions, SSP is about two orders of magnitude more expensive than terrestrial power. Even if significant technological advancements will result SSP arrays with higher levels (i.e. the "goal" level) of specific power, the space segment’s LCOE will still be about an order of magnitude more expensive than power generated on Earth. On the other hand, the system already is, and can more so be in the near future, a competitive energy source for expeditionary operations and as emergency event response. As said before, an SSP system adds the benefit of dynamic power allocation and is able to power extraterrestrial missions as well. Moreover, the spacecraft build and launch costs that will make the system economically competitive can be two to three orders of magnitude higher than predicted two decades ago [51]. In this respect, Caltech’s SSP program has made a significant advancement in enabling solar space power as a significant source of sustainable, clean energy. The following sections will detail some of the design choices which lead to the above results, with emphasis on parts in which I was involved. 3.3 System Level Design This paragraphs will detail some of the design choices which lead to the above results, with emphasis on the parts in which I had a significant contribution. Frequency of operation The selection of the frequency of operation is probably the single most important design choice for the RF part of the SSP system. It affects power conversion and transmission efficiency, antenna density and design complexity, and has significant implication on thermal dissipation and final weight of the integrated module. From raw efficiency perspective, it can be shown that the frequency of operation should be within the low-gigahertz range. We assume that power is converted to RF using a high-efficiency switching amplifier [52]–[54] where transistors are used as switches and passive devices are used for impedance matching. The passive 47 efficiency is, fundamentally, frequency dependent. In most cases, the limiting components are inductors, of which size generally decreases and quality factor generally improves with an increase in the frequency of operation. It can be shown [55] that if a PA is matched by 𝑛 passive sections to the system’s output, the matching impact on the total efficiency can be calculated as p√ !𝑛 𝑛 𝑃𝐸 𝑅 − 1 𝜂 𝑝𝑎𝑠𝑠𝑖𝑣𝑒 = 1 − , (3.16) 𝑄 where 𝑄 is the (frequency dependent) matching section quality factor and 𝑃𝐸 𝑅 (power enhancement ratio) is the ratio of the required power to the power generated over an easily realizable impedance (e.g. 50 Ω) assuming a peak voltage limited operation. A more intuitive and less quantitative definition of 𝑃𝐸 𝑅 is as follows: the optimal impedance shown to a PA depends on the supply voltage and output power - the higher the power, the lower the impedance. If this power should drive a transmission line or an antenna (usually, but not exclusively 50 Ω), then an impedance matching is required. 𝑃𝐸 𝑅 is the impedance ratio 𝑅𝑜𝑢𝑡 /𝑅𝑖𝑛 realized by the matching network. The passive efficiency therefore decreases with 𝑃𝐸 𝑅 and increases with Q, while different values of 𝑛 limit the designer to a specific range of realizable 𝑃𝐸 𝑅. Fig. 3.6 illustrates the achievable efficiencies for the required PER, given 𝑛 and 𝑄 = 𝑄 𝐿 , the quality factor of the matching network inductor. In contrast to the passive components’ behavior, the active components’ (switches) impact on efficiency deteriorate with frequency. The quantification is architecture and process dependent, but the fundamental reason is the increasing difficulty to prevent temporal overlap between the voltage drop along the transistor and the current flowing through it. The overlap manifests as power dissipation in the switch effectively increasing the loss. Figure 3.7 shows an estimate for the achievable drain efficiency of a 65nm switching PA, given off- and on-chip passives quality factors (50 and 20, respectively), and simulated switch efficiency for a 65 nm bulk CMOS process. Obviously, using high-Q, off-chip passives is favorable for the system performance, but is unacceptable from weight standpoint, where a 1 gr inductor will consume about 60% of the allotted weight of a 10 cm × 10 cm area of the goal system design of 1.6 gr. Keeping with on-chip passives, we see a plateau in the achievable drain efficiencies between 1 GHz - 10 GHz. With the above efficiency estimates, we can now compare the focusing capability at different frequencies. The first diffraction minimum at a distance 𝑅 from a circular 48 Figure 3.6: Achievable efficiency for given PER, quality factor, and number of output matching stages [55]. Figure 3.7: Power amplifier efficiency versus frequency as a combination of passive and active component efficiencies (Fig. courtesy of Dr. F. Bohn). 49 Figure 3.8: SSP array size and its far-field spot size versus frequency of operation (Fig. courtesy of Dr. F. Bohn). array with diameter 𝑑 is approximately [56] 𝐷 1 = 1.22 𝑅𝜆 𝑑 (3.17) in the far-field of array. Thus, higher frequency of operation results in a smaller collecting area on the ground. Interestingly, due to the square dependence of the far-field (Fraunhofer) region on the aperture [42] 𝑑2 𝑅𝑓 𝑓 = 2 , 𝜆 (3.18) the far-field distance of even a relatively small array at high frequency can be significant. For example, at 10 GHz, a 720 m array’s far-field is at approximately 35,000 km, as far away as a GEO orbit. Fig. 3.8 shows the beam size on ground for an array diameter with far-field at GEO versus frequency. One important remark about the far-field approach is that an antenna array does not have to operate at far-field. The beam can also be focused if operating in the near-field (Fresnel approximation), and the beam area can be approximated using (3.7). Thus, from focusing standpoint, higher frequency of operation is more desirable. Fig. 3.9 shows the attenuation of RF waves through the atmosphere. Notably, above 50 Figure 3.9: FCC’s graph of RF attenuation through the atmosphere [57][58] 10-15 GHz, millimeter-waves start suffering from significant attenuation. Therefore the frequency of operation should not be much higher than that. Lastly, the frequency of operation determines the amount of required antennas per unit area. Assuming a standard 0.5𝜆 spacing in vacuum between antennas, 𝑁, the number of antennas per unit area [ 𝐴𝑛𝑡𝑒𝑛𝑛𝑎𝑠/𝑚 2 ] is calculated as 𝑁≈ 𝑓2 0.152 (3.19) where 𝑓 is the operating frequency in GHz. Since the power per unit area is determined only by the solar power intensity in space, 𝐼 𝐴𝑀0 , each antenna radiates a power of 𝐼 𝐴𝑀0 . (3.20) 𝑃𝑎𝑛𝑡 = 𝑁 Fig. 3.10 shows 𝑁 and 𝑃𝑎𝑛𝑡 as a function of frequency. While working at low frequency allows for a simpler radiators array design, higher antenna count means that less power is dissipated by each antenna. This has two important implications: first, it requires lower 𝑃𝐸 𝑅 and thus allows to achieve higher conversion efficiencies for given on-chip passive quality factors. Second, since each PA dissipates less power, higher antenna count distributes the heat dissipation across the carrier sheet. 51 Figure 3.10: Change in (a) number of antennas per unit area and (b) power supply to be radiated by each antenna vs. frequency of operation. In space, heat dissipation to the environment is radiative (no convection) and thin metallic sheets are poor thermal conductors. Increasing the number of ICs per unit area alleviates much of the thermal dissipation challenge as will be shown later. Architecture and materials The architecture and materials for building a lightweight SSP spacecraft are divided into tile- and spacecraft-level. The first is handled by the solar structures and RF electronics teams while the latter is handled by the lightweight solar structures group. This chapter will briefly describe the spacecraft level design, survey the current and asymptotic weight goals, and detail the demonstration structures that were built at Caltech with currently available technologies. In order to minimize the array weight and ease its deployment, the SSP array is envisioned as a large sheet, assembled from flight-synchronized modules. Following the discussion of cost perspective, the array size is derived from the required power received and beam width on earth. Each module is a separate spacecraft, containing a large number of tiles, held together in groups (panels). Fig. 3.11 illustrates the array’s build and function. The formation of the whole structure in space is yet to be developed, but the deployment of each spacecraft has been discussed, proposed, and implemented as a 52 d PV RF (a) (b) Figure 3.11: Conceptual SSP array: (a) Array, spacecraft, panel and tile levels and (b) concept of operation of an SSP sheet PV-RF power conversion system. 1 m × 1 m prototype, non-functional structure [59] illustrated in figure 3.12. While this architecture fairly is developed, one drawback is the inconsistent power delivery capability throughout the day. If the RF and PV panels are on opposite sides, the system cannot both receive solar power and transmit it to Earth, when Earth is between the array and the sun (Fig. 3.13a). This effectively halves the power output or doubles the cost of the system’s space segment. There are several solutions in development to place RF antennas and PV panels on the same side of a sheet as shown in Fig. 3.13b. Such are low fill-factor antennas (wires), optically transparent ground planes, and flat photovoltaic cells. The unit cell itself is designed to maximize the specific power of the system in a progressive fashion. The initial design goal aims for the highest achievable specific power with current technologies. The asymptotic goal tries to extrapolate what will be available in the future and the implications on specific power. In parallel to those, a third design was built using available production materials to demonstrate and explore the system’s features and design space. The tile’s light weight is enabled by a single RFIC that performs most of the tile functions. In the final design stage this RFIC will contain, other than RF chains, a micro-controller on the same or on a separate die, a non-volatile memory, and power regulators, leaving only the antennas and a few capacitors off-chip. It will be mounted on an ultra-thin layer of polyimide and the board’s conductors will be made of aluminum, which offers superior mass 53 Figure 3.12: SSP spacecraft packaging: (a) Deployed, (b) collapsed plain, (c) folded inwards, (d) collapsed sideways and rolled, and (e) packed [59]. density over copper with negligible hit in conductivity. In order to further reduce weight, the PV cells do not cover the whole back side of the tile, but are made of stripes attached to the back of parabolic reflectors (blinds). The latter are designed such that their focal point is on the PV cells and light that hits them is completely concentrated there. From system-level perspective, attaching the PV and RF parts of an SSP system directly together is a major weight-saving concept. Otherwise, DC cables would be needed to distribute the collected solar power, with a significant hit on wither weight, efficiency, or both. The RF antennas, mounted on the other side of the tile, are fabricated on a second ultra-thin polyimide layer and are separated from the main board with an air gap, serving as the cavity or separation (depending on antenna type to be used) enabling the antennas to radiate. To minimize weight, the antenna layer will be suspended in air with a lightweight frame and "s" shaped springs made of fiberglass or other material. Tables 3.5 and 3.6 detail the complete estimate for a 10 m × 10 m tile materials as well as a spacecraft weight breakdown. An asymptotic estimate to the expected improvement over time of the tile weight was given in [40]. It is based on the estimate of the involved groups to the reduction in mass possible in the tile and spacecraft components, and is detailed in table 3.7. 54 Figure 3.13: Comparison of (a) a single-sided RF/PV vs. (b) a dual-sided RF/PV SSP spacecraft coverage [41]. Table 3.5: Breakdown of mass contributions and total mass of a 10 cm × 10 cm tile Layer Concentrator Reflective Concentrator Backing Front Emissive Layer PV Cell Tile Support Routing Layer Antenna Backing Antenna Conductive Si IC and Shield Carbon Fiber Frame Total Material Al Kapton SiO2 III-V, Cu Kapton Al Kapton Al Si/Al2 O3 Carbon Thickness [𝜇m] Mass [gr] 10 10 4 40 10 5 10 2 300/1000 Various 0.324 0.170 0.122 0.257 0.142 0.135 0.142 0.054 0.116 0.138 1.6 55 Table 3.6: Mass breakdown of a 60 m × 60 m spacecraft Component Mass (kg) Tiles Hub Strip structure (longerons and battens) 576 50 19 6 0.01 651 Booms Diagonal cords Total Table 3.7: Expected improvement in areal mass between SSP iterations PV [gr/m2 ] RF [gr/m2 ] Architecture 790 Mk 0 820 445 Mk 1 390* Mk 2 22 36.4* * Asymptote 11 13.4 * These are intended to use Perovskites which will reduce 𝜂 𝑃𝑉 from 28% to 20% While advancements in the development of materials and technologies are made, an SSP tile prototype, shown in Fig. 3.14, was built using existing technologies. This prototype will be discussed thoroughly in section 3.5. The prototype resembles the proposed final product, but its materials, dimensions, and weight differ in the following aspects: – The tile is designed for a single 16-output chip. Element spacing is chosen to be 0.6 𝜆, to minimize antenna coupling while maintaining reasonable grating lobes. Hence RF radiator size on tile is 7 cm × 7 cm. – The main board is fabricated using off-the-shelf polyimide (kapton) laminates. Fabrication and RF routing constrains its thickness to roughly 300 𝜇m. Metal layer thickness is off-the-shelf 17 𝜇m. – The PV cell design necessitates some on-board regulators to handle chip required voltage levels. – The photovoltaics are less efficient than the design goal and cannot supply the required power to the chip to function properly at AM0 solar power intensity. As a result, the finished size of the tile was increased to 16.5 cm × 10 cm. 56 Figure 3.14: A photo of an SSP tile prototype. – The finished system weight is about 16.2 gr. While this demonstration board is about 15 times heavier than desired, it is still more than an order of magnitude lighter than similar systems [60]. Later in this thesis, an expansion of the base design of this RF tile is used to build a flexible, fully operating phased array with 256-elements. RFIC thermal management There is a loss associated with any power conversion system due to the imperfect nature of electronic components. This loss manifests as heat generated by the power converter and dissipated to the environment through the following mechanisms: – Conduction: Heat interacts with matter and dissipates locally, thus elevating the material temperature. – Convection: Heat transferred by mass motion, where the heated mass moves away from the heat source and thus carries the heat energy away with it. In this context, convection usually accounts for the interaction between the static circuit board and dynamic surrounding air. – Radiation: Transfer of heat energy as electromagnetic waves, due to movement of charged particles in matter. In this context, heat transfer by radiation also accounts for heat transfer between circuit board and the environment. Thermal analysis reminder 723K 713K 193K 199K 57 (b) (a) • CST MultiPhysics used for simulation • 10X10cm of aluminum foil, 5um thick, radiating to one direction on (a) a square tile and Figure 3.15: IC temperature in space due to heat dissipation • Dissipated ~2W from ~3x3mm silicon piece (b) a circular tile. • Assumed: efficiencies - Solar=0.3 PA=0.5, Al emissivity=0.8, Psun=1.36[kW/m^2] • Also assumed cold background on non-radiating side (30K) The content of these slides is preliminary or provisional and is subject to revision. Not for general distribution. In space, heat conduction is assumed to be similar to Earth, however convection does not occur due to the absence of matter. The background temperature, relevant for radiative heat dissipation, is much lower than on Earth, especially for the spacecraft face that is not facing the sun. The total heat dissipated by RFIC due to DC-RF power conversion is: 𝑃𝑑𝑖𝑠𝑠 = 𝐼 𝐴𝑀0 𝐴𝑡 𝜂 𝑃𝑉 (1 − 𝜂 𝐷𝐶 𝑅𝐹 ) (3.21) qith the quantities defined in (3.2)-(3.4). To estimate the tile’s IC temperature, we assume that its surface area is 100 cm2 . 𝜂 𝑃𝑉 was assumed 30% and 𝜂 𝑅𝐹 50%, leading to 𝑃𝑑𝑖𝑠𝑠 of roughly 2 W. Thermal simulation was run using CST microwave studio with a 5 𝜇m layer of aluminum ground plane. The aluminum emissivity was assumed to be 0.8 on a single side to account for the fact that its back is blocked by PV structure. Fig. 3.15 shows the simulation results for square and circular tile structures. The circular tile is a simplified version for the thermal design optimization that will be described below. Clearly, this temperature far exceeds silicon ICs’ operating temperature range, and requires a more efficient thermal design. The most important observation is that the large temperature gradient is due to the poor thermal conductance of the thin aluminum and does not depend much on the radiative heat dissipation, which is set anyway. The solution is therefore to use a variable thickness ground layer as shown in Fig. 3.16. Thermal conductors can be modeled as equivalent circuit resistors [61]. We try to capture a steady state behaviour, and therefore we are not modeling heat capacitance here. In this case, a metal plane is equivalent to a series of resistors, with values which quadratically reduce with radius. Therefore, an improved thermal design will 58 Figure 3.16: Thermal optimization simulation setup. R IC H Al Ground (a) (b) dVn=dVn+1 Figure 3.17: Quadratic ground plane profiles. (a) Zero edge thickness. (b) Equal volume. utilize a varying-thickness ground plane, with a quadratically increasing thickness towards the tile center. Two analytical models are considered as illustrated in Fig. 3.17. The first profile has a quadratically increasing metal thickness from zero at the tile edge (“zero edge thickness”). The second profile keeps the total metal volume constant underneath any constant width annulus around the center (“equal volume”). As a reference, these models were compared to a discrete optimization simulation in which 5 concentric discs with varying height and radius are found to minimize the maximum board temperature. The optimizer uses Nedler-Mead algorithm and is set to preserve the total volume of used metal plane. Fig. 3.18 shows a point optimization and the differences in metal profiles for the three methods described above. After redistributing the metal ground profile, the RFIC temperature significantly drops to 395K or about 120◦ C, a high, but manageable value. Fig. 3.19 59 Figure 3.18: Varying ground thickness for each of the thermal conduction improvement schemes. shows how the maximum board temperature is varying with the amount of heat that each IC dissipates for the three proposed metal profiling methods. This sweep is an equivalent to the frequency of operation, where a higher frequency corresponds to more ICs per unit area and therefore less power dissipated per IC. These results confirm that the "equal volume approximation" is an adequate analytical method to improve IC temperatures by using a gradient ground thickness. The difference from lengthy, brute-force optimization is less than 10% with a much shorter simulation time. Fig. 3.20 shows, using the "equal volume approximation," how the amount (weight) of aluminum used for the ground plane affects the IC temperature. It can be further used as a thermal design guideline when the system performance/cost trade-offs are considered. Lastly, an RF tile with equivalent PV heat sources was simulated. This time the size is set to 6 cm × 6 cm, according to a frequency of operation of 10 GHz, with 4 × 4 antennas separated by 0.5 𝜆, and an RFIC that dissipates 0.72 W. Vertical "fins" with strip heat sources were added to the structure to emulate the PV cells. Each of them was set to dissipate 2 W according to a PV efficiency of ≈ 30%. Mock antenna patches were added in front of the IC ground Thermal analysis optimization • 60 Simulation Results: Maximum temperature vs. Single IC dissipated power (chips per tile) Optimization vs. Approximation 450 Optimization 430 Equal Volume Max Temperature [K] 410 Zero @ edge 390 370 350 330 310 290 270 0 0.5 1 1.5 2 2.5 Single IC dissipated power [W] (equivalent to chips per tile) Figure 3.19: Expected temperature as a function of power per chip, all ground leveling schemes. Thermal analysis optimization • Design-space mapping, by using equal volume assumption: Maximum temperature vs. Single IC dissipated power (chips per tile) 550 50mm^3 Al on 100cm^2 tile 25mm^3 Al on 100cm^2 tile Max Temperature [K] 500 100mm^3 Al on 100cm^2 tile 450 400 350 300 250 0 0.5 1 1.5 2 2.5 Single IC dissipated power [W] (equivalent to chips per tile) Figure 3.20: IC temperature as a function of power per chip for different ground metal volume, "equal volume" approximation. 61 Variable Height Ground Plane RFIC 338K PV heat source PV fins (Aluminum) Antennas sheet (Kapton) and mockup (Aliminum) Figure 3.21: Estimated temperature of tile with PV and RFIC heat sources in space. Figure 3.22: A basic rectenna design. plane and antenna emissivity is again estimated at 0.8 (black paint). The PV side emmisivity is assumed to 0.5. Fig. 3.21 shows the simulated structure and results. A maximum temperature of about 65◦ C is acceptable and demonstrates the viability of the tile design from the thermal aspect with regard to the cooling mechanism and choice of frequency of operation. Ground receiver array So far, the ground receiver part of the system is the least developed. Conceptually, it will be designed as an array of RF to DC converters (rectennas) that will collect and convert the transmitted RF power on Earth. The general structure of a single rectenna includes the receiver antenna, a low pass filter, diodes for RFDC conversion, and a filtering element to suppress AC components in the rectified waveform, and is illustrated in Fig. 3.22. Even though the basic concept is simple, the design of efficient RF-DC converters is challenging due to the non-idealities of physical components. The diode, which exhibits series resistance, non-zero built- 62 in voltage, and, at high frequencies, considerable contact inductance and junction capacitance, sets limits for both efficiency and feasible frequency of operation. Passive component losses, which result from the capacitors’ dielectric ceramic filling, the inductors’ skin effect, and the surface roughness of transmission lines, can also become significant in wavelength-scale RF circuits. Recent studies report efficient rectenna implementations in GHz range, achieving as high as 73%, 83%, and 60% at 2.45GHz [62], 4.5GHz [63], and 10GHz [64], respectively, and similar efficiencies are expected for the SSP ground receivers. Safety aspects RF radiation is generally defined as electro-magnetic waves with frequencies of 3 KHz – 300 GHz. RF radiation is non-ionizing, since the photon energy associated with EM waves at those frequencies is not high enough to pull electrons away from atoms and create ions [65]. Non-ionizing radiation has been shown to interact with biological tissue mainly via heat transfer. Studies have also reported other effects of exposure to RF radiation. Several examples are: in 1992, a large study by Chou et al. [66] investigated the potential effects of long-term microwave irradiation on rats, by exposing them to 0.4-W/kg SAR at 2450MHz for 13 months. It recorded various parameters, including behavior, blood chemistry/hematology, metabolism, and total body analysis, and found no definitive biological effect in rats chronically exposed to RF radiation at those frequencies. Another study by Lai and Singh [67] showed increased amount of single and double stranded DNA breaks in rats exposed to radiation resulting from whole body SAR of 1.2W/kg. However, an attempt by Malyapa [68] to measure similar results in alkaline comet assay under similar SAR rates while maintaining constant assay temperature, resulted in no significant difference from the control group. In 2010, the INTERPHONE study group published the results of a large scale study [69] that investigated a possible connection between cellular phone usage and brain tumors in 13 countries in Europe and Australia. The study observed no increased risk of glioma or meningioma to the average user and is referred here since cellular phones operate in GHz range radio frequencies. Other reported effects on humans include changes in the immune system, behavioral effects, neurological effects, and evidence for a link between microwave exposure and the action of certain drugs and compounds, all under specific exposure conditions [70]. Even though non-thermal biological effects of RF radiation were shown to exist, it is still unknown whether or not they impose a biological hazard. This fact has led regulators to adopt guidelines for maximum recommended RF powers 63 density exposure, which are derived from RF thermal effects on human body. For example, the American FCC recommends that professionals be exposed to RF radiation with a density of less than 50 W/m2 averaged over 30 minutes. In the case of a receiver ground station, the energy density is expected to be 50 W/m2 – within the FCC recommended limits. If RF radiation power density remains a concern, other measures can be taken, such as protective clothing. Also, since the transmitter is a directional antenna array, the main lobe carries most of the power. Therefore an area out of which the RF power density is negligible can be well defined for the convenience of the general public. 3.4 RFIC Design An SSP RFIC should perform as many of the system’s functions as possible with as few external components as possible. The main performance requirement is doing so accurately and efficiently. The RFIC therefore synthesizes a low noise clock from a low frequency reference, independently controls the phase and amplitude of its output channels, and drives its output antennas. Additional functions such as voltage regulation, biasing, and digital control and communication support the operation of the main system blocks. At a frequency of 10 GHz, the SSP spacecraft will have antennas with spacing of about 15 cm apart. The solar power supplied to the equivalent unit area is about 0.3 W, and about 87 mW (19.4 dBm) for each antenna PA, given a solar conversion efficiency of 25%. A small die on the order of 10 mm2 is a logical choice for an SSP RFIC. It will not be subject to significant stress when mounted on a flexible substrate and its size can fit about 16 transmit chains without unreasonable design complexity or thermal management. By synchronizing multiple RFICs to a single reference signal, this approach provides a building block to build highly scalable and potentially very large-scale phased-arrays [71]. The RFIC in Fig. 3.23 utilizes 17 on-chip PLLs performing a two-step RF power generation. The on-chip central, programmable PLL in Fig. 3.24 synthesizes a 2.5GHz RF signal from a low frequency, 5 MHz - 200 MHz external reference clock that is distributed to different RFIC units. The chip also utilizes buffers and a delay-locked loop (DLL) circuitry [72] to allow retiming and redistribution of the low frequency reference between chips (Fig. 3.25). This is crucial when large arrays scale to a size where it is impractical to use a single central clock source to directly drive all the system RFICs. The 2.5 GHz frequency generation and distribution will be described in detail in the next chapter. PV RF IC uC 64 4 Dig 2x Digital I/O Supplyregs regs Supply PWM 2 1.2V bandgap Clock distribution (H-tree) Fast-f Dig dig 2.5GHz PLL clock Register M Register generator U Register Register PWM in PWM rst Input/Fanout 2.5GHz clock buffer DAC Dig Dig ADC CP S 3 Ref in ADC dig RF out 4 Ioffset PFD 4x 4 X PWM counter 1.2V PWM/ fast-f ADC out Temp sense Loop H(s) Power Power Power Quadrant Power Quadrant Quadrant Quadrant 4 4 2x 4 10GHz, I/Q filterRF phase Phase data /4 freq sel Figure 3.23: A top-level schematic of the SSP RFIC. Trigger Reference in (5-200MHz) PFD CP LF switch Loop filter 2.5GHz dig Divide-by-N freq sel Figure 3.24: An RFIC centralized 2.5GHz output phase locked loop (PLL). dig Ref in Ref out The 2.5 GHz reference is distributed on-chipAnalog to four groups of four Digital (quadrants) PFD CP Delay Delay independently controlled RF chains (Fig. 3.28). Each of the four chains within a quadrant employs a second clock multiplier unit (CMU) to synthesize an output Digital Delay Control signal around 10 GHz. The CMUs also operate as programmable phase shifters by & Reset introducing a digitally controlled current offset to the multiplier charge-pumps, as shown in Figs. 3.26 and 3.27. The introduction of a phase shift through the CMU is simple and efficient. However, it requires a stabilization of the feedback loop and might be too slow for certain applications. Thus, the CMUs are followed by fast vector modulators as shown in Fig. 3.28, which can be programmed and pre-loaded at high speed. Each chain is completed by a power generation unit, shown in Fig. 3.29 (16 in total). dig Divide-by-N freq sel 65 dig Ref in PFD Analog Delay CP Digital Delay Ref out Digital Delay Control & Reset Figure 3.25: An RFIC delay-locked loop (DLL). dig PWM in PWM rst Register Register Register Register M U X DAC 2.5GHz clock 2x offset PWM counter PFD S CP Loop filter 10GHz, I/Q dig /4 freq sel Figure 3.26: Second ×4, 2.5 GHz to 10 GHz clock-multiplier unit (CMU). Trigger Reference in Each RF chain PA can be operated and controlled independently, however, within (5-200MHz) Loopas illustrated in 2.5GHz each quadrant they arePFD stacked CP from aLFDC perspective Figure 3.30. switch filter This allows for reuse of the current that is shared by the four cores, to bias the PAs at almost four times higher voltage and significantly reduce IR drops on the supply dig lines. Several versions of the RFIC were fabricated and in the latest version only two PAs were stacked on top of eachDivide-by-N other to improve channel-to-channel isolation freq sel and circuit stability, as shown in Fig. 3.31. A control algorithm is used to monitor and adjust the operating voltages of the amplifiers dynamically [73]. The final stage of each amplifier, where most of the DC-to-RF power conversion occurs is realized using a differential-cascode topology to guarantee reliability under load mismatch. dig The fabricated RFIC along with the physical locations of its blocks is shown in Fig. 3.32 Ref in Ref out PFD CP Analog Delay Digital Delay Control & Reset Digital Delay System Design - Tile 66 • X4 PLL phase shift with DC offset PS Qenable Vbias Q 2.5 GHz Reference I PFD QVCO ÷4 Th01F-4 Figure 3.27: CMU phase shift mechanism (Fig. courtesy of Dr. B. Abiri). 1.2V reference 2x 8 1V regulator PoR Chopper PA sup switch dig RF Phase out I/Q 2x 2.5GHz CMU 10GHz Rapid fcontrol Sense out Power Core RF out Sense out Power Core RF out Power Core RF out Power Core RF out Dig, 18 fast-f PWM 2.5GHz CMU 10GHz Rapid fcontrol Dig, 18 2.5GHz CLK in fast-f PWM 2.5GHz Dig sel CMU 10GHz Rapid fcontrol Sense out Dig, 18 PWM 2.5GHz ADC analog MUX ... Core supply & sensor values Readouts for uC CMU fast-f 10GHz Rapid fcontrol Sense out Dig, 18 PWM fast-f PA ground Figure 3.28: Block diagram of the power generation quadrature. This approach enables very large and highly scalable arrays, using a large number of silicon RFICs. The small component-count, predictable repeatability of manufactured parts, and feature-rich functionality make it economically attractive for a wide range of commercial applications. An interesting implication of this architecture is that there are broad delay variations in between various daughter cards due to low-frequency reference distribution length variations, as well as different transmission line lengths leading to the individual antennas, as shown in Fig. 3.33. The delay results from manufacturing variation, routing constraints, and board-level RF interference, and manifests as an absolute phase shift between radiating elements. Furthermore, as is the case with other 67 3V High Current Supply 1V regulated supply Driver supply reference 10GHz Supply regulator Driver RF network Power Amplifier Supply domain transition RF output network & balun RF out 10GHz Cascode reference High-voltage charge pump 2.5GHz clock 1.2V reference PVT independent /matched bias Driver supply reference 2x Dig, 16 DAC DC current sensor Sense out Core peak voltage sensor next PA supply rail Figure 3.29: Power amplifier block diagram. VDD+ Vref Vcas RF input (PLL) Vgbyp RF output Vref Vcas RF input (PLL) Vgbyp RF output Vref Vcas RF input (PLL) Vgbyp RF output Vref Vcas RF input (PLL) Vgbyp RF output GND Figure 3.30: Block diagram of four PAs stacked on top of each other from DC perspective [73]. reference distribution techniques, this is also prone to temperature and environmental variations. For example, at 10 GHz, where a typical on-board electrical length is 68 Low Frequency Reference Inter-IC Sync. Sys. Health Monitoring Delaylocked Loop φ Set 4X PLL Central PLL φ Set SPI Digital Interface 4X PLL SRAM IQ φ Rapid φ Control SRAM IQ PA φ PA Rapid φ Control …. (8 two-stack PA pairs for 16 total independently phase controlled outputs) Figure 3.31: Block diagram of an RFIC with two output PAs stacked from a DC perspective [74]. 1.5cm, routing differences of 1mm translate into a phase mismatch of more than 𝜆/8. In a large array, the phase differences between outputs are practically random necessitating a focusing approach that is oblivious to them. A general approach to the focusing of large scale phased arrays will be briefly discussed in the following sections. On-chip reference-signal synthesis Using a custom IC to manage the tile’s control and communication functions opens a range of possibilities, as well as imposes several challenges when scaling the system size to a larger number of synchronized tiles. Fig. 3.34 shows the conceptual reference and communication bus interconnect between the SSP array tiles. In this scalable array architecture, a single low-frequency reference clock is distributed to the tiles, where the high-frequency signals are synthesized using an integrated PLL and used for the coherent RF signal generation. The reference synchronization is in fact what allows the array tiles to work in concert, as illustrated in Fig. 3.35. One major challenge with this architecture is maintaining the timing accuracy of the reference signal in the distribution process. A central star or H-tree distribution is impractical in the case of a large scale array as the number of traces and the electrical load of all the driven elements become prohibitively large. On the other hand, sequential buffering of the reference suffers from large accumulated timing 69 ADCs, Bias CMUs, PAs, phase control, regulators digital/IO Phase Regulators, Cal Temp Sens DLL PLL Bandgap ref. Tx Channel Figure 3.32: Die photo of the phased array transmitter RFIC. deviations due to variations in the supply, temperature, and the driven load. While the latter is difficult to predict, and is dependent on the conditions of operation, an upper bound for the accumulated timing deviation can be estimated. A simplified physical structure of an inter-tile reference distribution scheme is shown in Fig. 3.36. Assuming that the noise sources of subsequent stages of reference distribution blocks (either on chip or discrete power splitters) are independent, the total noise of a square array with 𝐾 distribution stages is v u t 𝐾 h i √ √ 1 Õ 2 2 4𝑛 · (𝑛 𝑠𝑡𝑎𝑔𝑒 𝑘) + (𝑛 𝑠𝑡𝑎𝑔𝑒 2𝐾 + 1 − 𝑘) . 𝑛𝑡𝑜𝑡𝑎𝑙 = (3.22) 4𝑁 2 𝑘=1 Summing the series gives r √ (𝐾 + 1)(2𝐾 + 1) ≈ 𝑛 𝑠𝑡𝑎𝑔𝑒 𝐾 + 1. (3.23) 2𝐾 This is an upper bound because, in fact, the steering angle of a phased array is dependent on phase difference between elements. Therefore, there are correlated noise 𝑛𝑡𝑜𝑡𝑎𝑙 = 𝑛 𝑠𝑡𝑎𝑔𝑒 70 Ref Variations Output Variations 7cm 30cm (a) (b) Figure 3.33: Length variations due to (a) reference distribution routing and (b) output antenna traces. components within the clock distribution paths. The correlation can be significant; an extreme example is a single clock source driving multiple ICs. If the ICs do not add noise of their own, the clock source noise will not translate to any phase error at all. Finding how tight this upper bound is is an interesting and valuable future research problem. It can be shown [75] that for large arrays (𝐾 → ∞), the theoretical loss of efficiency Φ, due to uniformly, independently distributed random phase errors with a range of 𝛿𝑚𝑎𝑥 , is sin 𝛿𝑚𝑎𝑥 . (3.24) Φ(𝛿𝑚𝑎𝑥 ) = 𝛿𝑚𝑎𝑥 If the phase error is normally distributed, as is in the case of clock phase noise, then √ 𝛿𝑚𝑎𝑥 = 3 · 𝜎. (3.25) Fig. 3.37 shows a plot of (3.26) in percents versus the rms phase noise of an infinite array. By using (3.23) and (3.24), we can estimate the design specifications for a single tile reference distribution noise performance: a maximum of 5% efficiency loss is ≈13 degrees of rms phase noise. At 10GHz, the signal period is 100 ps so the phase error is 3.6 ps. For a 1000 stages of clock distribution then, this requires an integrated phase noise of ≈ 110 fs for each distribution stage. Another important performance metric is the phase that the on-chip synthesizer adds to the outputs. Assuming that the synthesizers on different chips are independent 71 Figure 3.34: Conceptual inter-tile communication and reference distribution (Fig. courtesy of Dr. F. Bohn). Figure 3.35: Clock distribution to CMOS-driven phased array. Module 72 2 2 2 1 2 1 0 1 2 1 2 2 …. 501 …. 2 …. 500 500 501 …. 1000 Figure 3.36: On-chip reference generation and distribution (daisy chain option) (Fig. courtesy of Dr. F. Bohn). from each other, the total phase noise added to the array is √ 𝑛𝑡𝑜𝑡,𝑐ℎ𝑖 𝑝 = 𝑛𝑡𝑜𝑡,𝑐ℎ𝑖 𝑝 𝐾. (3.26) For example, for a chip with integrated phase noise of 500 fs only as many as 𝐾 = 7.22 ≈ 50 chips may be used before the efficiency hit due to phase errors reaches 5%. This is significantly more restrictive than the requirement for the clock distribution scheme. Hybrid DLL Environmental variations, on the other hand can be mitigated utilizing a delaylocked loop (DLL) in the repeater buffer. While fundamentally sound, this approach presents new challenges since the low reference frequency, usually a few tens of MHz, necessitates a relatively large delay which can lead to unacceptable timing jitter. The SSP RFIC therefore uses a hybrid DLL architecture that utilizes several noise reduction techniques as well as a novel semi-digital loop control scheme with a single phase detection path. Moreover, the co-design of the DLL with the 73 Theoretical loss of efficiency due to random phase error 12 Efficiency loss [%] 10 8 6 4 Infinite Array 2 0 0 5 10 RMS phase error [o] 15 20 Figure 3.37: Phased array loss of efficiency due to the array’s phase noise (infinite array approximation) (Fig. courtesy of Dr. F. Bohn). subsequent PLL-based synthesizer is exploited to further reduce the overall timing jitter by proper alignment of the two phase noise transfer functions; one loop provides rejection over the frequencies where the other has a large noise contribution. This approach opens the design space, leading to superior overall performance. In a DLL, the output signal must practically be delayed by at least half a clock period compared to the reference in order to correct both negative and positive timing errors. A standard implementation does so with a single continuous delay line, which is usually the main noise contributor due to the large delay range it needs to cover. A hybrid DLL can solve this problem by using two different sets of delay elements, as shown in Fig. 3.38a,b. A digitally controlled delay line (DCDL) composed of low-noise fixed-delay elements is used for coarse delay tuning, while a short, continuously variable delay line (VDL) is used to fine tune within the digital segments. In order to achieve delay lock, we use an analog DLL architecture and continuously monitor its charge pump (CP) output control voltage (Vc) to adjust the required DCDL value. Initially, the up/down counter of Fig. 3.39b is set to fix the DCDL state, and the DLL loop of Fig. 3.38 continuously controls the VDL. If an unattain- 74 able VDL tuning value is required, the control voltage Vc will rail, crossing some lower or upper thresholds along the way. This activates the overflow detector of Fig. 3.39a to pause the continuous control loop, initiate a single increase/decrease of a DCDL cell, and restart VDL tracking. Unlike [76], we are not changing the continuous delay range by flipping a state machine to set discrete phase states, but are instead adding or removing a fixed amount of low noise delay as required. This significantly improves the noise performance. In addition, we are tracking the same edge in a monotonous, continuous, and overlapping manner—which, when combined with the fact that the DLL is a first-order control loop, guarantees its stability. The reset circuitry in Fig. 3.39c is crucial to temporarily disable the phase detector and force Vc to mid-supply when a DCDL shift occurs and is synchronized such that the phase detector starts at a consistent state once the VDL tracking restarts. The noise-optimized, pseudo-differential delay elements of Fig. 3.40 also allow tracking of the falling edge of the output clock, which effectively reduces the minimum delay required by T/2 and enables usage of the same delay line at lower reference frequencies. This architecture offers enhanced robustness because (1) it necessitates neither lock detect indication nor dual phase detection circuitry as in [77] [78], (2) the small signal gain is identical for all DCDL values, and (3) the DCDL state changes in single up/down steps. The latter indicates that subsequent VDL tracking starts from a well-defined, nearby position, unlike a digital controller with automatic delay step adjustment. Our implementation favors clock distribution applications where lock time is not a major consideration. If necessary, fast lock is achievable with an a priori estimate of the DCDL delay step values and external programming of the up/down counter state. Integrated PLL The hybrid DLL was co-designed with its intended load PLL. In order to minimize the DLL in-band noise, its loop filter bandwidth was optimized to be around 1MHz to sufficiently reject the delay line noise while maintaining a relatively flat noise shape around the PLL loop filter knee frequency. The PLL is the first frequency conversion stage of a building block for large-scale phased arrays and as such, was designed for optimal noise performance, given the chosen design process. The output VCO has a fixed frequency of 2.5GHz and the device size is chosen for minimum noise with the required output amplitude and power consumption. The use of both NMOS and PMOS cross-coupled pairs (Fig. 3.41) has several advantages. The startup gain is almost double because these are two parallel positive feedback blocks (negative-𝑔𝑚 ), 75 VDL Reference In Phase Detector (PFD) CP DCDL Reference Out Vc LPF Reset PFD Reset Vref Δtana Overflow Detector Up/Down Counter Initial Count (a) Vout t Δtdig td,ref (b) t Figure 3.38: Hybrid DLL function. (a) Schematic and (b) hybrid phase tracking. the swing is almost rail to rail, and since there is no drain inductor, the low-voltage parallel mim-capacitors are not at a risk of voltage breakdown. The frequency divider is implemented using a standard 2/3 divider topology [79], and the phased-frequency detector is a standard D Flip-Flop state machine [80]. The loop filter and charge-pump current values are digitally variable to set the optimal bandwidth and phase margin depending on the input reference frequency. This was done by using a capacitor bank for the loop filter as illustrated in Fig 3.42. A simulation test-bench was built in Keysight-ADS to optimize the loop filter values and Table 3.8 summarizes the optimization result. Another important noise source is the PLL reference spurs. These result from periodic variations of the VCO control voltage which exist when the PLL is locked with a net-zero charge injection per-cycle. Integer reference spurs should be minimized because they might become a significant spectral disturbance when present at the output of a large-scale transmitter array. There are two main reference spur sources for an integer-N PLL as detailed in Fig. 3.43. The first source is a mismatch between the charge-pump "up" and "down" current 76 Figure 3.39: Circuit description of the (a) overflow detector/actuator, (b) DCDL MUX set, and (c) reset circuits for a hybrid operation. Table 3.8: Optimization values of variable PLL loop filter and charge-pump current Ref. Freq. [MHz] ICP [mA] CLPF1 [pF] CLPF2 [pF] CLPF3 [pF] RLPF1 [Ω] RLPF2 [Ω] Loop BW [MHz] Jitter [fs] 10 25 50 125 250 0.415 0.73 1.67 1.56 0.83 25 24.5 20 15 15 600 600 600 580 600 11 11.2 5.3 1 1 2000 1450 650 470 450 150 150 150 150 150 0.38 0.8 1.63 2.8 2.85 1000 500 288 183 160 77 Figure 3.40: Hybrid delay line structure. VDD Trigger PFD CP Vc Loop filter LF switch Vout,n Vout,p dig Divide-by-N freq sel Figure 3.41: PLL VCO. RLPF2 RLPF1 ICP CLPF2 CLPF1/2 CLPF1/2 CLPF3 Figure 3.42: A variable loop filter for the optimization of the PLL noise performance at different frequencies. 78 Iup Idn Iup Idn T Both on (intentional) Icp T Both on (intentional) t (a) Idc Icp t (b) (Iup-Idn)av=0 Both on (unchanged) Both on (assume perfect match) t (c) T (Iup-Idn)av=0 T Idc Leakage compensation t (d) Figure 3.43: Reference spur sources: (a) Charge pump mismatch and (b) DC current leakage. Periodic charge transients on control voltage line (c) due to up/down mismatch and (d) DC leakage. sources. This is due to the charge-pump dead-zone prevention [80] mechanism that forces "up" and "down" sources to be open simultaneously for a short period of time. The stronger current source injects excess charge which is eliminated in the steady state by the weaker source remaining open for a bit longer. The second spur source results from DC leakage of thin oxide devices due to tunneling effects. Every cycle there is a small leakage current that discharges the loop filter and VCO capacitors, and the loss of charge is prevented in the steady state by excess injection from the charge pump. The ripple that is created by both of the mentioned effects translated into output spurs. To minimize leakage-related spurs, the PLL uses mostly thickoxide capacitors. This complicates the design and increases its size because the capacitance density is significantly smaller than that of thin oxide devices. The PLL also employs a pass-through switch to negate the effect of the charge-pump current mismatch as shown in Fig. 3.44, similarly to [81]. The switch pass-through start and end time are digitally variable to optimize the spur rejection operation. The PLL is fabricated in a 65nm bulk CMOS process. It occupies 0.4 mm2 of active area and consumes about 6mA from a 1V supply. Fig. 3.45 shows the PLL die photo. The PLL is characterized with a reference frequency of 50 MHz. Fig 3.46 79 Trigger PFD CP Loop filter LF switch dig Divide-by-N freq sel IUP (Iup-Idn)av=0 CP CP Ripple UP Switchout Enabled Current enabled SW T DN CIN t COUT IDN Figure 3.44: Pass-through switch structure for up/down mismatch spur prevention. (b) Figure 3.45: PLL die micrograph. 80 (a) (b) Figure 3.46: PLL spur reduction switch measurement. shows the PLL output spectrum and switch operation for phase-noise rejection. The switching operation lowers the output spurs by about 10 dB. Fig. 3.47 shows the harmonic rejection of reference spurs as a function of the switch start and stop times. A heat map of the output reference spur harmonics was plotted versus the digitallyvariable start and stop times of the pass-through switch (Fig. 3.47). This is useful in order to understand the timing sensitivities that may change due to production variations. Such sweeps can be used in the future as a basis for digital calibration of the desired reference spur levels. The measured integrated phase noise in Fig. 3.48 is strikingly similar to the simulation. The measurement differs from the simulation in the low-frequency range due to the reference oscillator and charge-pump noise slope that were not taken into account in the simulation. The high range of the noise measurement is limited by the instrument noise floor. Both mismatches from simulation are small enough so as not to be noticeable in the integration. Reference distribution measurements The DLL was fabricated in a 65nm bulk CMOS process (Fig. 3.49). It occupies 0.036mm2 of active area, and its joint operation with the PLL was characterized at an output frequency of 2.5GHZ with the input reference ranging from 27MHz270MHz. Fig. 3.50 shows the delay locking mechanism while the DLL drives either 50W or 10pF loads. The control voltage Vc in Fig. 3.50a overflows and resets until it reaches the necessary DCDL value, while fine-tuning persists indefinitely. The delay between the output and reference signals (Fig. 3.50b) was calculated from the 81 Output harmonic content, high frequency range vs. switch pulse start/end time, 0.6ns step/state Figure 3.47: PLL reference spur levels for different digital settings of start/stop times of the pulse. 82 PLL phase noise vs. frequency, low bit, ~300fs Figure 3.48: PLL phase noise PSD measurement vs. simulation waveforms’ zero-crossing points, emphasizing how proper sizing of the overlapping DCDL step size and VDL range allow for proper operation of the circuit. The SSP is intended to operate in space and phase setting variations are expected to be slow, on the order of minutes, the expected temperature fluctuation is therefore low - less than 10◦ C in steady state, and the measured closed-loop control voltage tracks the temperature at a rate of 2.4mV/◦ C. The nominal control voltages for locking are 340mV and 660 mV when counting up and down, respectively, and the overflow detector has a nominal hysteresis of 30 mV. Therefore, temperature variations are not expected to toggle the digital counter and add additional, unaccounted noise. In our clock distribution scheme, static buffer phase offset is programmatically removed when the array is calibrated and therefore not of a major concern. Fig. 3.52 shows how the DLL degrades the noise performance of a reference clock source by examining the phase noise spectral density profile of the cascaded application blocks, measured using a Keysight PXA N9030B signal analyzer (Fig. 3.51). Notably, the frequency band of interest is above 1kHz, where phase errors are presumably correctable by external phased array adjustment algorithms, and below 10MHz, far away from the load PLL loop filter knee frequency. Figs. 3.52a and 3.52b clearly show how the PLL loop filter rejects most of the DLL noise, and thus 83 (a) Figure 3.49: Hybrid DLL die photo. brings it to contribute as little as 323fs rms jitter in the relevant frequency band. These measurements were repeated at different frequencies between 27MHz and 270MHz, and a summary is shown in Fig. 3.53. The lower and upper frequency ranges are limited by the maximum DCDL delay and overflow actuation timing accuracy, respectively. Fig. 3.53b demonstrates how this DLL is advantageous in that an increase in the frequency of operation decreases the number of DCDL elements that participate in the delay chain, and thus the power consumption remains roughly constant. Fig 3.53c emphasizes how the system is optimized for 50MHz operation. At lower frequencies, the high DCDL count adds more noise to the output, while at higher frequencies the subsequent PLL loop filter has little effect on noise rejection. Because the end goal is the phased array reference distribution scheme of Fig. 3.35, noise performance was characterized for several, cascaded DLLs, as shown in Fig. 3.54, If the noise of each stage is uncorrelated with the others, the total noise measured at the output of an N DLL cascade is expected to be: 2 2 2 2 𝑛𝑡𝑜𝑡𝑎𝑙 = 𝑛𝑟𝑒 (3.27) 𝑓 + 𝑛𝑚𝑒𝑎𝑠 + 𝑁 · 𝑛 𝐷 𝐿𝐿 where 𝑛𝑚𝑒𝑎𝑠 is the measuring instrument noise, 𝑛𝑟𝑒 𝑓 is the reference noise, and the single device noise can be estimated from the slope of the linear fit. Fig. 3.55 shows the linear behaviour of the DLL cascade jitter variance at different frequencies and the resulting rms jitter is summarized in Table 3.9, showing good agreement with the single device measurements of Figs. 3.52b and 3.53c. (b) [V] 84 5 10 (a) Time [μs] DCDL cell delay, 270ps VDL positive overlap, 60ps (b) Time [μs] (c) Time [μs] Figure 3.50: Hybrid lock process at different time scales. (a) Loop filter control voltage, (b) time delay between reference and output clocks, and (c) time domain waveforms (adjusted). Figure 3.51: Cascaded PLL and DLL measurement setup. 85 Figure 3.52: Noise performance. (a) 50MHz DLL phase noise and rms jitter, and (b) 2.5GHz post PLL phase noise and rms jitter. The red curves are the rms measurement uncertainty. '//3HUIRUPDQFH9V5HI)UHTXHQF\ >@ D      ,QYHUWLQJ 1RQ,QYHUWLQJ   506-LWWHU>IV@ >P:@ E      F :LWKRXW3//DWUHIIUHT :LWK3//ILOWHUDW*+]     5HIHUHQFH)UHT>0+]@  Figure 3.53: Performance vs. frequency. (a) Participating DCDL cell count, (b) power consumption of participating DLL blocks, and (c) rms jitter within the 1kHz - 10MHz band. 86 Figure 3.54: Cascaded DLL jitter (a) test setup and (b) photo. Table 3.9: DLL noise performance, based on Fig. 3.55. Reference Frequency [MHz] RMS Jitter, 1kHz-10MHz [fs] RMS Jitter, 1kHz- 𝑓𝑟𝑒 𝑓 /2 [fs] 27 733 809 50 456 685 100 402 698 200 268 481 270 261 549 Summary The task of distributing a low noise reference to very large-scale phased arrays is challenging because it does not enjoy the shorter period times of GHz range clocks. Table 3.10 shows a performance comparison of the hybrid DLL/PLL scheme with prior state-of-the-art at similar frequency ranges, and demonstrates how combining new circuit architectures with application-aware design can result in an order-ofmagnitude improvement over the state-of-the-art. 87 Figure 3.55: Cascaded DLL jitter. (a) 1kHz - 10MHz measurement, and (b) 1kHz𝑓𝑟𝑒 𝑓 /2 measurement. Red and blue curves indicate locking to inverted/non-inverted output, respectively. Chip level measurements Additional measurements were carried out to finalize the RFIC characterization. Fig. 3.56 shows the PA output power and CMU phase shift range, covering more than 360◦ with a constant amplitude. Fig. 3.57 shows the chip phase noise PSD and integrated phase noise, both of which within the required specifications. 3.5 Tile-Level Integration and SSPP Demo The self-contained RFIC is the centerpiece of a unit building block tile for the modular system. Each tile incorporates 16 single polarized radiators in a 4 × 4-grid, where each RFIC output drives a radiator (3.58). The system size can rapidly scale by repeating the tile pattern on a large flexible laminate (Fig. 3.59). The element spacing is 18mm (0.6 𝜆), and the total tile size is 7 cm × 7 cm. Even though the RFIC could be assembled directly on the flexible board, doing so will introduce significant stress to the soldered bumps which might lead to mechanical failure. In addition, it will require a very tight control of the flexible PCB metal traces, which might be costly for large sheets. For this reason, a thin rigid adapter board (interposer, Fig. 88 Table 3.10: DLL performance comparison table Frequency range Comparison frequency RMS jitter [ps] In band RMS jitter Power consumption [mW] Supply voltage [V] Technology process [CMOS] Die area [mm2 ] This work JSSC 05’ [76] TCASII 07’ [78] TCASII 09’ [82] CICC 13’ [83] 27-270MHz 0.252GHz 32320MHz 0.023GHz 80450MHz 50MHz 270MHz 250MHz 200MHz 50MHz 180MHz 0.685 0.55 5.25 4.44 7 (approx.) 2.3 0.33ps 0.26ps NA NA NA NA 2.25 3 1.2 15 (320MHz) 0.4-3.6 26 1 1.8 2.5 1 1.5 65nm 180nm 250nm 90nm 130nm 0.036 0.046 0.07 0.005 0.08 Figure 3.56: RFIC output: (a) power and (b) phase shift range [84]. 89 Figure 3.57: RFIC single channel output phase-noise PSD (Fig. courtesy of Dr. F. Bohn). 3.60) is used to mount the integrated circuit on the flexible circuit board. The small interposer only slightly adds stiffness to the flexible circuit board, and is helpful in fanning out the RFIC digital control lines and in converting the radiator 50Ω transmission lines to show an optimal impedance of 75Ω to the PA outputs. The simulated and measured interposer S-parameters in Fig 3.61 agree well with each other and the good matching and inter-channel isolation assist in maintaining the PA stability. This RFIC is designed to work in space, and while it is functional without additional cooling mechanism, a heatsink is needed to reach its performance specs in a terrestrial environment. Antenna design The SSP array is supposed to be packed compactly before deployment. This requires the use of either very low profile or collapsible antennas, which must be lightweight as well. The challenge is that in order to function properly, an antenna needs some space from the signal ground plane. For dipole style antennas, this space should be in the order of 𝜆/4, or 7.5 mm at 10 GHz in vacuum. Patch antennas permit thinner spacing (in the order of 𝜆/10), but usually exhibit narrower bandwidths. Both types of antennas require a robust feed design at RF frequencies which might collide with the requirement for a lightweight structure. Practically, rigid low profile antennas 90 Component Side Antenna Side Ref. In MCU 70 mm RFIC RFIC 0.6λ (18 mm) PLL DLL Tx Channel Figure 3.58: A flexible phased-array transmitter unit-cell (tile). Antenna Sheet Main Board Scalable Sheet Data/Ref. Bus Tile Unit Cell Figure 3.59: Multiple tile unit-cells combined on the same flexible laminate to form a larger array. 91 Interposer RFIC SPI bus RF outputs RF match             5HWXUQ/RVV6LP 5HWXUQ/RVV0HDV &KDQQHO,VRODWLRQ0HDV  >G%@ >G%@ Figure 3.60: Chip-board interface with a small rigid interposer.        )UHTXHQF\>*+]@ D   ,QVHUWLRQ/RVV6LP ,QVHUWLRQ/RVV0HDV     )UHTXHQF\>*+]@ E  Figure 3.61: Chip interposer measuring (a) return loss and (b) insertion loss. 92 Figure 3.62: Bandwidth, directivity, radiation resistance, and efficiency with respect to surface waves excitation for a resonant square element as a function of dielectric thickness for different 𝜖𝑟 [85]. use a dielectric material to decrease their electrical length and reduce their size. Consequently, the EM field in the dielectric increases (for a given radiation power) so their loss increase as well [85]. Bandwidth is also affected. As an example, Fig. 3.62 illustrates the impact of the dielectric material on the performance of a rectangular patch antenna. An SSP spacecraft antenna should also be conducive to scaling of the array’s size in terms of performance, manufacturing, and assembly capability. For our design, we use collapsible antennas as shown in Fig. 3.63. They are printed on a thin, 50 𝜇m single-layer polyimide laminate and are designed as patches to reduce the required spacing from the ground plane, in order to improve the structural strength of the assembly. Vacuum is used as separation from the ground plane to reduce loss and increase the bandwitdth. This antenna has four square patches cut away from it to decrease the metal weight and reduce its size, which in turn also improve the isolation between the array’s antennas. A series inter-digital capacitor is used to resonate the equivalent series inductance of the antenna lead to match it to the frequency of operation. The single antenna pattern is illustrated in Fig. 3.64. The patch antennas are intended to be used as single sheets, assembled 93 Figure 3.63: Vacuum-suspended patch antenna: (a) designed and (b) fabricated/measured [84]. Figure 3.64: Flexible patch antenna pattern [84]. on top of the main board sheet. The antenna structure is placed flat on the main array board, with the leads soldered to the main board’s footprint. It is then lifted so a vertical, matched feed excites the antenna, as shown in Fig. 3.65. After lifting, "s" shaped flexible springs are placed between the antennas and ground plane to support the structure. Those "s-springs" are flexible enough to allow for both sheets to be pressed (collapsed) together and rolled into a package. Due to the height difference between the two layers, the structure had some limit on the minimum radius of curvature of the packing as shown in Fig. 3.66. One challenge with finite antenna arrays is that due to coupling and reflections, the antenna pattern in the array might differ from the standalone pattern. Fig. 3.67 shows such a difference using simple patch antenna designs. The implication is that usually there will be some difference between the expected and measured performance. In addition, this calls for a calibration procedure that will take these 94 Antenna Sheet Feeds Flex Circuit Board Radiating Structure on Antenna Sheet Feed Trace on Flex Board Figure 3.65: Flexible patch antenna sheet and feed above ground. Figure 3.66: Antenna packing curvature limit due to different radii of the two flexible sheets. factors into account. Such a calibration and focusing procedure will be described later, when an integration of several tiles to a larger system will be described. Alternative antenna designs The patch antenna sheets approach was fabricated and was shown to work. However, it has a few drawbacks: the antenna feed lines are thin and difficult to solder, and the use of two sheets severely limits the flexibility of the assembly. In addition, differences in the rigidity of the main and antenna boards deform the assembled antennas and create uneven locations where the antenna height above ground is significantly different than intended. It is therefore desirable to explore additional antenna design and assembly schemes. 95 4 x 4 Finite Planar Array Figure 3.67: Simulated change in element pattern when placed in a finite-size array with a finite ground plane. Vertical thin sheet The most promising antenna structure is a vertically attached thin sheet structure as shown in Fig. 3.68. The radiating structure can be designed as a dipole and the ≈ 𝜆/4 distance from ground can be used for impedance matching. Physically, the thin sheet can be supported with a specifically molded fiberglass structure to maintain flexibility without deteriorating the electrical performance. A test antenna was designed and measured (Fig. 3.69). It exhibits a wider band matching and the simulated radiation pattern is wider than the patch pattern. The assembly can be simplified almost to the level of an SMT process (pick and place) with a proper support structure. The drawback of this antenna is its height, which might be unacceptable for some applications. It might also be unsuitable for terrestrial applications where wind might causes the antennas to wobble. Helical spring Another tempting option is the use of helical spring antennas. These can be more rigid than vertical thin films with similar performance as shown in Figs. 3.70 and 3.71. This antenna EM field is circularly polarized, and will require a receiver with circularly polarized antennas as well. The main drawback of this design is that the antenna’s structural stability trades off with its flexibility. When the antenna is 96 Physical Support (a) (b) Deployed Folding Packed GND plane (c) Figure 3.68: Vertical sheet antenna concept. packed, it is compressed and the stored energy in multiple antennas might lead to unacceptable mechanical stress on the packed spacecraft sheet. Designing a dual polarized equivalent structure is challenging as well. High dielectric patch While using high dielectric patches above the ground plane in order to reduce the antenna size might be unsuitable for space-power applications, it can still be useful for communications and sensing, or for applications where structural integrity is more important than performance. The antenna size can be further reduced to ≈ 𝜆/4 on the expanse of efficiency by using a PIFA [86] structure. Materials selection In order to reduce the system’s weight as much as possible, a thin flexible PCB substrate is used for the main and antenna boards. The planar antennas require only a flexible substrate bonded to a single copper layer. The thinnest commercially available substrate is a 50 𝜇m polyimide layer with a 12 𝜇m copper clad. The main board build is dependant on the level of the integration of the SSP RFIC and on several high-frequency design choices. Currently, a microcontroller is not integrated in the RFIC package. This requires a large number of digital signals to be routed on board. The output RF transmission lines which are routed to the antenna feeds are designed with a specific characteristic impedance and are matched 97 Figure 3.69: Vertical sheet antenna (a) test structure (the plastic support should be removed or changed in the final design), (b) input matching, (c) antenna pattern 0◦ , (d) antenna pattern 90◦ . Deployed Folding Packed GND plane Figure 3.70: Collapsible spiral spring concept. 98 (a) (b) (c) (d) Figure 3.71: Collapsible spring antenna (a) test structure (the plastic support should be removed or changed in the final design), (b) input matching, (c) antenna pattern 0◦ , (d) antenna pattern 90◦ . to the antenna impedance, which is in turn matched to the free-space impedance. Practically, microstrip transmission lines are the only feasible choice because they need a single ground plane, provide almost ideal isolation to the line’s backside, and do not require a large number of ground-vias. Three parameters can be modified to allow the use of a thinner dielectric layer effectively lowering the board’s aerial mass: – Characteristic Impedance: Lowering this parameter allows the use of a microstrip with a higher width/height ratio. This, however, results in a higher transformation ratio from the set free-space impedance, lowering bandwidth and efficiency. 99 Figure 3.72: Fabrication options for a flexible 4-layers PCB. – Line thickness: Lowering this parameter allows the use of a thinner substrate for a set characteristic impedance, whith some hit in efficiency as well. It is constrained by the fabrication process tolerance. – Dielectric constant: Lowering this parameter increases the vertical electrical length and allows to use thinner substrate for a given transmission line characteristic impedance. The dielectric constant of polyimide is about 3.5 and reducing it further requires the use of specialty materials which are costly and usually weaker mechanically. While future design iteration may allow to implement the SSP tile on a 2-layer circuit board, currently 4 layers are needed. The board can be fabricated with commercially available single- and double-layer laminates as illustrated in Fig. 3.72. Since the transmission lines function is crucial to the system performance, the fabrication option described in Fig. 3.72 is preferred. The implication though is that buriedvias cannot be used in the design. This is another reason that microstrip lines are used. The microstrips are designed with a 50 Ω characteristic impedance on a DuPont™ Pyralux® TK which is polyimide infused with teflon. The 2-layer laminate has a dielectric constant 𝜖𝑟 =2.5. This allows the use of transmission lines of 100 𝜇m, within fabrication tolerances, with a dielectric thickness of down to 75 𝜇m to separate it from the ground plane. The copper traces were neither plated or covered with isolating laminate (coverlay) to guarantee that they perform as designed. The 100 finished 4-layer board has an areal density of roughly 0.1 gr/cm2 . A reduction in weight can be achieved by perforating the ground plane to reduce the copper weight of the board. This has minimal implication on the antenna performance if the holes are much small and closer to each other compared to the transmitted wavelength. RF measurements The fabricated flexible RF antenna was characterized using a mechanically scanned near-field range [87]. Functionally, a phased array should be able to perform steering of the main lobe in a tangible fashion. In terms of performance, the array output power and EIRP need to be measured. Measurement Setup The near-field range uses a vector network analyzer (VNA) to excite an antenna under test, (DUT) and to read the received power in a pre-characterized antenna probe. The probe location can be swept mechanically to measure a 2-D field intensity and phase. The measurement can be either in the near (Fersnel)- or far (Fraunhoffer)field of the DUT and a far-field pattern can be computed mathematically later in either case. The whole setup is placed in an anechoic chamber to prevent reflections that will degrade accuracy. This allows to obtain a plethora of interesting data regarding the DUT, including complex field components, directivity, polarization, beam steering capability etc. Active antenna arrays that generate the output signal from a low frequency reference require a minor adaptation in order to be measured using this range: since a VNA performs a single-frequency measurement, its output signal must be divided down to the antenna’s reference frequency, and the on-chip synthesizers must be set with an equal multiplication ration to avoid erroneous measurement. The measurement setup is illustrated in Fig. 3.73. The flexible phased array was characterized using the near-field range with a near-field probe at 30 cm away from its plane. The probe used is an E-field linearly polarized antenna, which can be rotated 90◦ around its normal axis to obtain the complex field components. The required phases for the antennas were set using the individually controlled CMUs in each of the RFIC’s output channels. The array was measured around 9.8 GHz which is slightly offset from the design frequency of 10 GHz due to small antenna detuning. 101 Flexible Phased Array Probe Antenna Clock Ref. Freq Div. Excitation Readout VNA Calibration and Phase Setting Array Control Unit (ARM MCU/ FPGA/ PC) NSI Antenna Measurement Figure 3.73: Array pattern measurement setup. Phase Steering For a uniform array, the element phase difference 𝛽 required to generate a maxima of the array factor at an angle 𝜃 𝑚 from the normal to the array plane is 𝛽= 𝑑 · 2𝜋𝑠𝑖𝑛(𝜃 𝑚 ) 𝜆 (3.28) where 𝑑 is the element spacing and 𝜆 is the radiated wavelength [42]. For an array operating at 10 GHz with 0.6 𝜆 between elements, this is ≈108◦ of phase difference. As mentioned before, this should be the phase shift at the antenna output, and there may be large static and dynamic phase offsets between each output channel. In order to overcome the unknown phase offset, the antennas’ phases were initially calibrated using a straightforward phase sweep over all of the 16 output channels’ digital settings. The required phase for maximum power at broadside were also estimated using a 3-D EM simulator [88] and the result is shown in Fig. 3.74. It is noteworthy that, while this method works, it is inefficient and unpractical for larger arrays. A better approach for focusing and calibration will be described later, 102 Figure 3.74: Simulated phase of each antenna output for broadside radiation [84]. Figure 3.75: Array broadside pattern [84]. where a 256-element array will be presented. The resulting radiation pattern was measured, and is shown in Fig. 3.75. Using the same phase sweep procedure, the array’s beam was directed at 30◦ left (𝜑 = 0◦ , 𝜃 = 30◦ ), and later at 30◦ up (𝜑 = 90◦ , 𝜃 = 30◦ ) as a demonstration of beam-steering capability (Fig. 3.73 shows the choice of direction). Fig. 3.76 shows the measured x- and y-components of the E-field for those steering angles. The patch antennas are linearly polarized and the measured radiation pattern is mostly an E-field along the y-axis as expected. 103 (a) (b) (c) Figure 3.76: Broadside array fields recorded in 2-D [84]. Table 3.11: Measured (simulated) pattern data for broad-side beam (𝜑 = 0◦ , 𝜃 = 0◦ ) Normalized intensity [dB] Largest sidelobe [dB] Half-power beamwidth [Deg.] 𝐸 𝜃 , 𝜑 = 0◦ 𝐸 𝜃 , 𝜑 = 90◦ 𝐸 𝜑 , 𝜑 = 0◦ 𝐸 𝜑 , 𝜑 = 90◦ -18.19 (-20.21) -18.19 (-20.21) -0.12 (0) 0 (0) -10.92 (-12.54) -11.09 (-14.31) -24.64 (-36.99) -24.64 (-38.04) 23 (22) 20 (21) - - By performing a near- to far-field transformation, the far-field radiation properties of the tile are obtained. Fig. 3.77 shows a comparison of the measured versus simulated steered antenna patterns. Tables 3.11, 3.12, and 3.13 compare the data of the measured radiation patterns to simulation. The measurement and simulation show good agreement in terms of the radiation patterns, half-power beamwidth, radiation efficiency, and sidelobe levels. The near-field range can generate 3-D holograms of the radiated fields in space by performing multiple 2-D measurements along the z-axis. This is a valuable capability for near-field applications where a beam is focused in space rather than steered to the far-field (infinity focus). Fig. 3.78 illustrates the field evolution of the three generated beams, which allows a better understanding of the array performance and phase search procedures. 104 Figure 3.77: Steered beam pattern (a) up and (b) left [84]. Table 3.12: Measured (simulated) pattern data for left-steering (𝜑 = 0◦ , 𝜃 = 30◦ ) Normalized intensity [dB] Largest sidelobe [dB] Half-power beamwidth [Deg.] 𝐸 𝜃 , 𝜑 = 0◦ 𝐸 𝜃 , 𝜑 = 90◦ 𝐸 𝜑 , 𝜑 = 0◦ 𝐸 𝜑 , 𝜑 = 90◦ -13.33 (10.14) -24.7 (-14.11) -13.03 (-14.09) -14.04 (-24.38) 0 (0) -28.33 (-29.09) -28.36 (-37.08) - - -11.55 (-10.58) 25 (24) - 105 Table 3.13: Measured (simulated) pattern data for up-steering (𝜑 = 90◦ , 𝜃 = 30◦ ) Normalized intensity [dB] Largest sidelobe [dB] Half-power beamwidth [Deg.] 𝐸 𝜃 , 𝜑 = 0◦ 𝐸 𝜃 , 𝜑 = 90◦ 𝐸 𝜑 , 𝜑 = 0◦ 𝐸 𝜑 , 𝜑 = 90◦ -21.77 (-31.51) -21.77 (-31.51) 0 (0) -12.41 (-26.95) -9.25 (-18.65) -29.03 (-39.88) -20.48 (-10.28) - - - -8.57 (-10.6) 23 (24) Figure 3.78: Phased array transmitter tile broadside hologram shows the evolution of the radiated field in space [84]. Power Measurement Even though the tile array has 16 radiating elements, the maximum radiated power was obtained with only 12 elements turned on. This is probably due to thermal sensitivity of the RFIC and maybe some marginal stability resulting from all 17 on-chip PLLs working and pulling each other to some extent. The raw output of each PA measured about 50 mW and the loss associated with the interposer (1-2 dB in the measured version), transmission lines (2-3 dB), and antennas (<1 dB) results in an output power of about 10-20 mW per antenna. The total power in the main lobe is estimated at 19.2 dBm, slightly lower than the expected of 12 output channels maybe due to heating and element-to-element non-uniformity. The tile’s EIRP in the frequency range of 9.4 – 10.4 GHz is shown in units of dBW in Fig. 3.79 with the four elements in the corners turned off. A nearly constant maximum EIRP of +38.2 dBm is achieved at 9.56 – 9.72 GHz with an EIRP of +37.1 dBm at 9.8 GHz. Later iterations of this design have improved both the interposer and transmission lines losses, have reduced the output loss, and enabled a stable operation with all 16 elements turned on. 106 Figure 3.79: Phased array transmitter tile EIRP (image reproduced from [84]). Solar integration The flexible phased array tile was integrated with PV cells as a proof-of-concept lightweight SSP spacecraft building block. The structure includes three major parts as illustrated in Fig. 3.80b: an antenna sheet fabricated on a lightweight single copper layer polyimide laminate, a 4-layer carrier board with an SSP RFIC and voltage regulators, and PV concentrators. The latter are parabolic reflectors with a high efficiency solar cell attached onto their back that use lightweight reflective materials to reduce the PV cells’ weight and cost, as shown in Fig. 3.80b. The antenna board is attached to the carrier board by flexible carbon-fiber springs that demonstrate its deployability, and is enclosed in a thin frame so it does not collapse. Unfortunately, the photovoltaic concentration scheme is extremely sensitive to mechanical deformation and manufacturing variations. In order to make certain that sufficient power is supplied to the RFIC to guarantee its functioning the tile area was increased for the demonstration purpose from 7 cm × 7 cm to 16.5 cm × 10 cm. It should be stressed, however that this is an integration issue and not a fundamental limitation of the design. Fig. 3.81 shows the finished tile. 107 Incident light PV Blinds DC lines IC Regulators Dig. PV Cell RF transition RFGND Compound Parabolic mirror RF Board GND Antenna microstrip lines 3mm Antennas (a) Thermal Conduction (b) Figure 3.80: Integrated tile: (a) structure and (b) PV reflector concept. (a) (b) (c) Figure 3.81: Integrated RF-PV tile. (a) Completed demonstration board, (b) antenna sheet, and (c) weight of the assembled board. 108 AM0 light source Integrated PV/RF tile PV Blinds DC lines IC Regulators Dig. RF transition RFGND RF Board GND Antenna microstrip lines 3mm Antennas Radiated RF power LED indicator Receiver antennas (a) (b) (c) Figure 3.82: Testing an integrated RF-PV tile under AM0 light source. (a) Measurement setup, (b) demonstration of RF lighting an indicator LED. (c) Power is not transferred when line-of-sight is lost. The RF-PV functionality was tested under a light source with AM0 intensity directed at the solar concentrators. A simple rectenna-array board with an indicator LED is placed on the other side of system and the transmitted RF power is strong enough to light it at a distance of about 20 cm away as shown in Fig. 3.82. This proof of concept demonstration showed that efficient wireless power transfer can be done with structures that are about two orders of magnitude lighter than the ones used in previous works. Thus this is an important step forward to building economically viable space solar power systems. 3.6 System-scale Integration While the demonstration of a flexible phased-array building block unit is valuable, scaling the system size presents additional significant challenges, notably when compared to similar arrays without beam-steering capabilities [89]–[91]. Distributing a reference signal over large distances results in attenuation and added noise due to the loading of the clock lines, as discussed in section 3.4. Transfer of data to a large number of ICs is either done in parallel, which requires additional on-board real-estate, or serially, which slows down the programming speed or requires an increase in data throughput. The alignment and assembly of a large antenna sheet requires a robust manufacturing process to avoid local deformations in the deployed array. Power distribution might not be a challenge for SSP applications where the 109 PV unit cells supply the power to each tile locally, but other applications might suffer from significant IR losses if they use long DC lines for power distribution. Additionally, a simple phase sweep procedure is impractical to use for array calibration and focusing due to exponential growth in the possible phase states. The following section will present the design and measurement of a 256-element, 16-RFIC phased array that was built from the SSP tile, and will include details regarding the design challenges and measured performance. Main board design The main board is designed using the same 4-layer fabrication process that was used for the single tile demo. As a first step towards a scaled-up system, we use a commercially available flexible-PCB laminate from DuPont™ , Pyralux® AP[92], which is a copper-clad polyimide core. The polyimide has a dielectric constant of 3.4, which requires the use of a 100 𝜇𝑚 laminate and slightly increases the system’s aerial mass over lower dielectric constant materials. On the other hand the copper adhesion is significantly stronger than Pyralux® TK, for example. this proved better for an initial assembly. This 256-element array is still small enough such that a single low cost CMOS-level pierce-gate oscillator can drive all its RFICs simultaneously at 50 MHz. An EM simulation [93] was run to predict the drive level at the IC input. The reference distribution is designed as an H-tree to provide a matched reference clock to all the ICs. It is noteworthy to remember that, due to production tolerances and PCB design constraints, there might be a residual delay between the ICs that translates to a non-negligible phase difference at 10 GHz. Further increase in the board size might require additional measures as described in section 3.4 to guarantee a low-noise, low-power clock distribution to all the array RFICs. In order to increase the write speed to the array, a field programmable gate array (FPGA) is used as a communication interface to the array with 16 SPI interfaces that are synthesized in hardware for parallel data transfer. It is important to remember that even though an FPGA can output a parallel bitstream, a CPU (or a thread for that matter) that controls it can only process data in series. Therefore this approach makes sense only if the CPU speed is much higher than the SPI interface. Here we are using a xilinx zync® board [94] with an integrated CPU working at 667 MHz to write to a several-MHz SPI module so the previous requirement is fulfilled. 110 Front Side FPGA - X16 SPI - Power Calibration Alorithm Algorithm 50MHz Phase Array Clock SPI Clock, X16 Data In/ Out, LE Unit Cell Figure 3.83: An assembled flexible phased array transmitter. The power strap DC power is not distributed on the 4-layer flexible circuit board, but instead brought to each sub-unit individually from a 2-layer flexible skeletal structure called the power strap. The mass-saving power strap is made using an inexpensive, nonimpedance-controlled substrate with less precise manufacturing standards than the flexible circuit board with 10 GHz transmission lines. The power strap board is shown in Fig. 3.84. The power strap input voltage is 1.8V, which powers the RFIC’s stacked PAs directly, and is doubled and regulated to provide other voltage levels needed by the RFIC and local MCU. High-current switches allow the power strap board to power the tiles from a single shared supply or from individual supplies located nearby. The local, individual power option is intended for use in conjunction with photovoltaic cells, which would mount on the opposite side of the planar array, away from the radiators [95]. This capability allows for distributed powering of the array, avoiding heavy, high current carrying wires. Figs. 3.84 and 3.83 illustrate the component-side of the 16-tile phased array and add details about the assembly of the reference clock, data, and power supply to all the array tiles. Antenna sheet and assembly The single-chip, 16-antenna design was scaled to a single 30 cm × 30 cm array of 16 × 16 radiators. Around the feed of each radiator, there is a cut in the thin 111 Figure 3.84: Power strap and supply interface for the flexible phased array transmitter. polyimide layer with small spacers that should be detached after assembly (Fig. 3.85) to enable the lifting of the antenna sheet. Soldering the antennas to the main board requires a special attention. The antenna leads are 100 𝜇m thick lines, that should be aligned and remain in place with a 30 cm × 30 cm board throughout the assembly process. Clearly, assembly by hand is impractical and will be impossible with larger array sizes. Here we use a "sandwich" concept in which the antenna and the main board are fixed together with solder paste in between, and put with a rigid aluminum fixture in a reflow oven, as shown in Fig. 3.86. This approach can presumably scale with the oven size, or even be implemented using a cylindrical rolling mechanism to process very long sheets. The initial assembly attempt yielded about 85% of the antennas successfully reflown to the main board, and the rest were re-worked manually. While not yet perfect, this made the assembly of the entire array much more manageable. Focusing There are several challenges in calibrating large phased arrays to deliver maximum power to a target device [96]. Most notably, the receiver unit must have a dynamic range large enough to sense small phase changes while not saturating when the array is fully optimized as illustrated in Fig. 3.87. Inter-element coupling and system nonlinearities (e.g., synthesizer frequency pulling) can present additional challenges. Flexible arrays add another layer of complexity because each element may have a different radiation pattern when the array is deformed and mechanical vibrations can add significant noise to the optimization process [97]. To mitigate these issues, we 112 Feed Spacers Reflow Pad Raw Antenna Sheet Figure 3.85: Antenna sheets: (a) a raw sheet and (b) a close-up on the board interface. utilize a novel search algorithm to find the optimum phases of groups of elements – each group is constructed by an appropriate 2-D orthogonal matrix (which, for instance, can be generated from Hadamard matrices) to form an orthogonal basis. Fig. 3.88 shows several examples of how to change the phases of groups of array elements simultaneously to increase the transmitter’s output variations and overcome the receiver sensitivity limits. In this manner, in the beginning of the optimization, we search over large variations of small groups of elements (coarse optimization), and in its end, we search over small variations in large groups of the array elements (fine optimization). This approach equalizes the amount of received power changes due to large and small phase sweeps to alleviate the receiver dynamic range requirements with a reasonable optimization time (1000-2000 steps for a 256-element array). Using an N-ary search avoids potential convergence issues associated with other optimization and focusing algorithms in a noisy environment (e.g., gradient decent). To perform a beam optimization, a small rectenna board is placed in front of the phased array and in each iteration, it feeds back a relative power reading to the optimizer. The latter then reprograms the array element phases, takes the next reading, and repeats. It is noteworthy that this method allows to optimize power delivery in the near-field, and that the optimizer can be implemented to work at tens of MHz on an FPGA, for example, to allow real-time power delivery optimization. Fig. 3.89 shows the optimization setup and an exemplary optimization sequence of 113 Cut-Outs RFIC, Interposer, Heatsink, SMD Components Main Baord Solder Paste Aluminum Fixtures Antennas Feeds Antenna Board (a) (b) Figure 3.86: Antenna sheet assembly. (a) Schematic description and (b) a demonstration of the assembly process. Large Variations Array Elements Receiver (a) Small Variations (b) Figure 3.87: The challenges in calibration of large arrays. (a) Physical problem setup and (b) implication on receiver dynamic range. 114 (a) (b) (c) Figure 3.88: Selecting groups of elements for phased array calibration/focusing: (a) half the array elements and (b) fourth of the array elements. (c) An example for a selection of groups of elements in a 16-element array to span an orthogonal phase Beam focusing - Implementation space. Phase Setting Array Control Unit (ARM MCU/ FPGA/ PC) 3 Power Receiver (Rectenna) Power Read (DC) 2.5 Readout Voltage [V] Flexible Phased Array 2 1.5 1 0.5 0 200 400 600 800 1000 1200 1400 1600 Mask Iteration Th01F-4 Figure 3.89: Phased array focusing setup (left) and results (right). 15 the flexible phased array. Beamforming To demonstrate the flexible phased array’s beam-forming and beam-steering capabilities, the array was calibrated in 5 different steering configurations using the previously described method. The focus point was steered broadside, as well as left/right/up/down to demonstrate 2-D beam-steering. The radiation pattern was measured using the mechanically scanned near-field range in Fig. 3.73, and then 115 transformed to a far-field pattern. The scan range of the near-field range limits the measurement to 14 degrees of elevation and 40 degrees of azimuth in the far field, with non-physical transform effects occurring at the extremes of the view width. The measured far-field radiation patterns in Fig. 3.90a-e show sidelobe levels below 7 dB and demonstrate a successful beam forming. The sidelobe levels would be reduced if the optimization target distance had not been constrained by available measurement space. The power in the broadside-focused beam main lobe was calculated by integrating the area under it and scaling the result by the maximum measured power density at the range probe. This power estimate is pessimistic because it assumes that the initial probe location was indeed at the maximum of the main lobe, and it neglects the losses due to the non-isotropic probe pattern. Nevertheless, under these constraints, we calculated a main focal-point power of 0.8W at a distance of 2 m. Deformation correction For use in deployable and conformal systems, flexible phased arrays must be able to correct their radiation pattern if their mechanical shape is deformed. Here, we deform the array convexly to demonstrate this ability, as shown in Fig. 3.91. Figs. 3.92a and 3.92b clearly show how the original phase settings that were used in the flat array to generate a broadside main lobe result in a scattered pattern when set here. The array is then re-focused to correct the aberrations introduced into the pattern by the shape change, and to find the optimum phases to recreate a broadside main lobe. Fig. 3.92c shows the result of the re-focusing, proving our ability to regenerate the desired pattern for a mechanically deformed array. Elevation (deg) 116 a. 5 0 -5 Elevation (deg) -20 -10 Elevation (deg) 20 b. 0 -5 -10 0 Azimuth (deg) 10 20 c. 5 0 -5 -20 Elevation (deg) 10 5 -20 -10 0 Azimuth (deg) 10 20 d. 5 0 -5 -20 Elevation (deg) 0 Azimuth (deg) -10 0 Azimuth (deg) 10 20 e. 5 0 -5 -20 0 dB -10 -10 dB 0 Azimuth (deg) 10 20 -20 dB Figure 3.90: Antenna pattern of a steered phased array beam: (a) Broadside, (b) up, (c) down, (d) right, and (e) left. 117 Deform c. (b) Elevation (deg) (a) 5 Figure 3.91: A flexible phased array transmitter: (a) flat and (b) deformed. 0 -5 b. Elevation (deg) -20 -10 0 Azimuth (deg) 10 -10 0 Azimuth (deg) 10 20 5 0 -5 c. -20 0 dB -10 dB 20 -20 dB Figure 3.92: Deformation correction. (a) Focusing, (b) deformation, and (c) refocusing of a deformed flexible phased array transmitter. 118 Chapter 4 SYNCHRONIZING RF PHASED ARRAYS WITH LIGHT 1 4.1 Introduction As active phased arrays become larger, synchronizing the operations of the the array elements becomes more challenging. Synchronization is done either directly with a reference at the output frequency, or indirectly, with a low frequency clock distributed between the RFICs which synthesize the required output signal from it. Each method has its advantages and drawbacks which make is suitable for different applications. Direct and indirect clock distribution Direct clock distribution is in theory desirable from system complexity and noise perspectives. Since no frequency multiplication is done, all the array’s output chains are driven circuits, operating far above 1/ 𝑓 noise corner. As such, their noise is set by the thermal noise of the amplifier which is dependent on its bandwidth, and is usually much lower than the noise added by on-chip synthesizers. In addition, the reference phase noise is correlated between all the outputs and therefore does not manifest in the beam-steering, which depends on the phase difference between the elements. The array also does not suffer from PLL-related frequency pulling and locking-related instabilities. The theoretical advantages however are hampered by practical difficulties. In the GHz range, generation and distribution of high frequency clock is inefficient and signal loss increases as the array grows in size. The cost of a high frequency material might make it unsuitable for certain applications and cable weight may be prohibitive in the case of large sparse arrays that are distant from each other. In order to enjoy the noise performance of a driven circuit, the driving signal must be large enough compared to the noise floor, which requires a power-hungry clocking scheme. Lastly, implementing a complete multi-output RFIC to reduce complexity means that there may be a significant feedback from the RFICs outputs to its input, which increases the risk for undesired oscillations. For these reasons, direct distribution of clock reference is usually used in classical defense and space applications where lower efficiency, cost, and post fabrication manual tuning are tolerable, and the addition of components (discrete PAs, etc.) is acceptable. 1 This work is done in collaboration with C. Ives and A. Khakpour. 119 This architecture is however unacceptable for many commercial applications, in which the economics of the system determine its feasibility. Indirect frequency distribution at a low frequency is simple at the board level and allow to implement large parts of the systems on a low-cost substrate. Frequency generation at those frequencies, usually in the order of 10s of MHz is simple and accurate through the use of quartz-crystals. The clock distribution scheme however becomes difficult with increase of array size, which unacceptably loads the clock source. This issue was thoroughly discussed in section 3.4 and calls for further inspection of additional reference distribution schemes. 4.2 Theoretical Background Electronic clock distribution schemes In its simplest form, an on-board trace can be modeled as a capacitive load. This approximation holds if the source is operating at a frequency with a wavelength much longer than the line. The power required to drive the line is determined by the driven voltage swing, 𝑉, the frequency of operation, 𝑓 , and the total capacitance associated with the line length 𝐶 𝑃𝑐𝑎 𝑝 = 𝐶𝑉 2 𝑓 . (4.1) Here we assume that long lines are buffered such that the low frequency assumption remains valid when the array grows larger. The capacitance per unit length can be calculated from 2.37 or numerous other sources [98]. Capacitively terminated traces can be driven by a resonant line as well. This is a less-standard design approach and though deserves detailed investigation, it will not be considered for the current comparison. A high frequency signal can drive long lines if the latter are designed as transmission lines and are terminated with a matched load. The power must be split to each element (or an IC controlling several elemenets) and the splitters themselves add some loss that usually increases with frequency. Since all the power is presumably delivered to the load, the power dissipation is determined by the required SNR at the load and the RF lines loss. For an input power of 𝑃𝑐ℎ𝑖 𝑝 delivered to 𝑁 RFICs, with a total line length of 𝑙 to each RFIC, with loss of 𝛼𝑙 per unit length, power dissipation associated with the distribution line is 𝑃 𝑅𝐹 = 𝑁 · 𝑃𝑐ℎ𝑖 𝑝 . 𝑙 · (1 − 𝛼𝑙 ) (4.2) 120 Buffer Line Source Split Source Line Line and Buffers Input Capacitance Rline Cline (b) (a) Figure 4.1: High frequency clock distribution schemes: (a) RF based and (b) laser based. The phase noise PSD in rad2 /Hz of an amplifier with a noise figure 𝐹, due to thermal noise is defined by [99] 𝑘𝑇 𝜙2𝑃𝑆𝐷 = 𝐹 · , (4.3) 𝑃𝑐ℎ𝑖 𝑝 with 𝑇 the environment temperature and 𝑘 Boltzman’s constant. The integrated phase noise in radians in a bandwidth 𝐵 is q 𝜙 𝑅𝑀𝑆 = 𝐵 · 𝜙2𝑃𝑆𝐷 , (4.4) or in seconds, given the signal frequency 𝑡 𝑅𝑀𝑆 = 1 . 𝜙 𝑅𝑀𝑆 · 𝑓𝑐𝑙𝑜𝑐𝑘 (4.5) Fig. 4.1 illustrates the general configurations of matched and capacitively loaded distribution networks. For simplicity, we assume that both networks use an "H-tree" architecture and that the capacitive network buffers are not constrained to be in the phased array RFICs. Optical clock distribution Laser can be used as a clock source by incorporating a photodiode in each RFIC and using a fiber as the distribution line. The required source power in this distri- 121 PD TIA Laser Source Fiber Figure 4.2: Laser clock distribution block diagram. bution scheme is mainly determined by the power that needs to be absorbed in the photodiode in order to be converted to an electrical signal with sufficient SNR for the phased-array output chain. For an output power of 𝑃𝑐ℎ𝑖 𝑝 delivered to 𝑁 RFIC PD with conversion efficiency 𝜂 𝑃𝐷 , the power dissipation associated with the clock distribution is 𝑁 · 𝑃𝑐ℎ𝑖 𝑝 . (4.6) 𝑃𝑙𝑎𝑠𝑒𝑟 = 𝜂 𝑃𝐷 It is important to note that for the same SNR, the required 𝑃𝑐ℎ𝑖 𝑝 might be significantly higher than an electrical RF signal due to the PD efficiency. However, the loss associated with an optic fiber is negligible over very large distances, so a scaling limit exists where it is beneficial over RF power distribution. In addition, the cost of a high-performance PCB substrate may be prohibitive for the latter in largescale commercial applications. Fig. 4.2 illustrated the optical reference distribution concept and its loss sources. Performance comparison Fig. 4.3 compares the three reference distribution methods in terms of estimated power dissipation versus the number of driven ICs, for a given noise performance. In order to do so, we make several simplifying but realistic assumptions regarding the other design variables. We want to draw conclusions for an SSP system, operated at 𝑓 𝑅𝐹 =10GHz, but also for 5G applications around 𝑓 𝑅𝐹 =28GHz. The low-frequency signal is assumed at a frequency of 50MHz. Each IC is assumed to drive 4 dual polarized antennas 𝜆/2 apart. Both RF and optical sources will be assumed at a frequency of 𝑓 𝑅𝐹 /2. Reasoning for this design choice is given in the conclusions of this section. The distribution line will be assumed as an H-tree for all the 122 schemes, designed on an FR-4 board with 𝜖𝑟 =4.5 or Rogers RO4350B with 𝜖𝑟 =3.5 for a capacitive or a matched load, respectively. The requirement for integrated phase noise will be 100fs in order to be competitive with recent state-of-the-art works. Since all those circuits use an indirect reference, they all require an output synthesizer. Recently, numerous PLLs were demonstrated around these frequencies with various reference sources, all achieving roughly 60fs of integrated phase noise [100]–[102]. The Synthesizer contribution is therefore assumed similar and is neglected for comparison purposes. Both a PD with a TIA and an RF LNA will be treated as tuned amplifiers with a noise figure of roughly 6dB and bandwidth of about 5%. Both assumptions are reasonable for a few stages of tuned amplifiers at this frequency. There are two length quantities that need to be calculated to estimate the clock power dissipation for the various methods, as shown in Fig. 4.4: the total length of traces in an H-tree, and the trace length from the clock source to a single chip. For a scale factor 𝑁 = 1, 2..., the number of chips in the array is 𝑁 𝑅𝐹 𝐼𝐶 = 4𝑁 and the number of chips per array side is 𝑁 𝑠𝑖𝑑𝑒 = 2𝑁 . For 2 × 2 antennas per chip, there is a distance of 𝜆 between chips and a total side size of 𝑑 = 𝜆𝑁 𝑠𝑖𝑑𝑒 . The trace length to each RFIC grows with N as 𝑙 𝑅𝐹 𝐼𝐶 = 𝑁 Õ 𝑑 1 𝑑 𝑑 + + ... + 𝑁 = 𝑑 . 𝑛 2 4 2 2 𝑛=1 (4.7) Summing and substituting 𝑑 gives   1 𝑙 𝑅𝐹 𝐼𝐶 = 𝑑 · 1 − 𝑁 = (2𝑁 − 1)𝜆. 2 (4.8) The total trace length grows with the array size as 𝑙𝑡𝑜𝑡 = 𝑑 𝑑 1 𝑑 1 𝑑 1 · 3 + · · 3 · 4 + · 2 · 3 · 42 + ... + · 𝑁−1 · 3 · 4𝑁−1 . 2 2 2 2 2 2 2 (4.9) Summing and substituting 𝑑 gives 𝑙𝑡𝑜𝑡 = 3𝑑 𝑁 Õ 2𝑛−2 = 2𝑁−1 (2𝑁 − 1) · 3𝜆. (4.10) 𝑛=1 Table 4.1 shows the calculated variables for each of the reference distribution option as well as the size scale for which using an optical reference becomes more efficient than an RF reference. A few conclusions could be drawn from this power estimate calculation. Notably, with a low frequency reference, the capacitively loaded scheme is by far the most 123 Figure 4.3: Comparison of distribution network power loss for different distribution schemes at (a) 28GHz and (b) 10GHz. 124 All Lines Length To RFIC (a) (b) Figure 4.4: Counting the (a) total length of reference distribution lines and (b) distance from centralized source to a single IC. Table 4.1: Calculated quantities of reference distribution power dissipation. Quantity Reference Frequency [GHz] Wavelength [cm] 𝑃𝑐ℎ𝑖 𝑝 [dBm] Required PN at IC [dBc] RO4350B loss [dB/cm] Antennas @ equal power Side length @ equal power [cm] Value 28GHz 14 1.07 -8.4 -129.5 0.15 16,400 Value 10GHz 5 3 -3.9 -134 0.05 17,600 68 200 efficient in terms of power dissipation. However, this comes at the expense of added noise, as shown in (3.23). In fact, for very low-noise applications like high throughput 5G communications, the noise added by even 3 stages of low noise buffer with integrated jitter of 50fs can exceed the specifications. RF power distribution is more efficient than its optical counterpart at small scale due to fairly low PD efficiencies on silicon. At a larger scale, optical reference distribution prevails because its power dissipation grows like 2𝑁 , the number of RFICs, while the RF power dissipation grows like 22𝑁 due to the line loss. In terms of cost, high performance RF material is one- to two- orders of magnitude more expensive than low cost FR4 and optic fibers, so it might be unsuitable for high volume commercial applications. There is another subtlety that is crucial to the understanding why an optical reference distribution is desirable. One way to significantly reduce the RFICs’ added phase noise is to use low multiplication ratio synthesizers. This allows for a high bandwidth of VCO noise rejection, and the noise of the source is 125 In Path 28GHz PLL Tx φ X8 PD ÷N φ Figure 4.5: Optical reference chip top block diagram. correlated between all the ICs so it does not contribute to the output phase error. The higher the reference frequency, the higher the loss in the PCB transmission line, and using an optical scheme is more favorable. Another consideration in favor of optical reference distribution is in other architectures where array elements are distant from each other. Examples are sparse arrays with large separations between the array parts, coherent combination of distanced phased arrays, and synchronization between distant parts of large sensor networks, for which cable loss, size, or weight is unfeasible. 4.3 Chip Design In order to demonstrate an optical reference distribution system, we designed a fully integrated optically driven, 8-channel phased array transmitter RFIC. It is fabricated in a 65nm bulk-CMOS process and has three distinct parts as illustrated in Fig. 4.5. Despite the fact that the smaller the multiplication ratio the better noise performance we get, we chose for demonstration purposes a reference frequency of 3.5GHz with a multiplication ratio of ×8 to 28GHz, to be able to implement a robust PLL that will not risk the complete system. Input stage design To take full advantage of CMOS integration, we implemented a photodiode on the fabricated ICs. While this allows to interface a photodetector on-chip without any additional process modification, the silicon band gap forces the system to use (mostly) visible wavelengths. The design of visible-light PDs is popular in home networks [103], vehicular [104], and visible light communications [105], and the design tradeoffs are well-understood [106]. A PD circuit model is illustrated in Fig. 4.6 with the following technology dependent elements: 126 Cp PAD P+ S N+ T I S T I P+ La Ra P-Well N-Well Cl Rl S T I N+ TS P+ I IPD P-Well Rnw Csub P-Sub Figure 4.6: Small signal model of a CMOS PD (recreated from [106]). – 𝐶 𝑝 , The parasitic capacitance between N+ and P+ electrodes – 𝐿 𝑎 , Accounts for the phase delay between voltage and current due to ionization – 𝑅𝑎 , Accounts for the finite reverse saturation current and the field dependent velocity – 𝑅𝑙 , 𝐶𝑙 , The capacitance and resistance of the depletion region – 𝑅𝑛𝑤 , The N-well resistance – 𝐶𝑠𝑢𝑏 , The N-well/P-sub junction capacitance. We are using a 3-finger, N+ /P-well, with a shallow trench isolation (STI) guard ring and a deep N-well (DNW) isolation. The design process started with an estimate of the technology layer structure and doping (Fig. 4.7), and was followed by layout construction and simulation in a dedicated software tool [107] to estimate the PD current versus input power, and the parasitic frequency dependent response which expresses mainly as shunt capacitance. Fig. 4.8a,b shows the simulation results and Fig. 4.9 shows the PD final layout. The photodiode size is 45𝜇m × 45𝜇m with an equivalent capacitance of about 500 fF which can be easily tuned on-chip, and a large enough cross section, to interface with an external fiber. The PD responsivity is estimated from Fig. 4.8b. An initial estimate of input power that will guarantee the proper operation of a 100𝜇m × 100𝜇m PD was 100 W/cm2 . For the simulation parameters of Fig. 4.8b, this is equivalent to an input power of 169 𝜇W. The output current is 10 𝜇A and therefore the expected output current is 60 mA/W. Contrary to standard serial optical links, a reference clock operates at a single frequency. This opens the design space to the use of narrow-band amplifiers to work with a given PD at higher frequency than dictated by its output capacitance, or a wide-band TIA 127 Figure 4.7: A cross section of doping concentrations for PD design (Fig. courtesy of C. Ives). Current vs. Optical Intensity for a 13µm x 13µm PD @ -6V Bias Current [A] Capacitance [F/m2] Capacitance vs. Reverse bias for a 50µm x 50µm PD @ 7GHz Reverse Bias [V] (a) Optical Intensity [W/cm] (b) Figure 4.8: Photodiode (a) capacitance density and (a) responsivity simulations (Figs. courtesy of C. Ives). bandwidth. The input chain is shown in Fig. 4.10. The PD parasitic capacitance is resonated with an inductor at its cathode, and a digitally selectable capacitor bank is used to ensure that the input is tuned to the desired frequency of 7GHz. A common-source differential amplifier is used as the first stage of the TIA-LNA to minimize the integrated noise at the input chain bandwidth. It is followed by two inverter-based amplifiers and a digital divider to bring the input to a rail-to-rail swing with a frequency of 3.5GHz as required by the integrated PLL. The input LNA is employing a negative-𝑔𝑚 cell in parallel with the amplifier tank to artificially boost its gain as shown in Fig. 4.11. The subsequent stages use a common-mode feedback amplifier to ensure the operating point of the inverters (Fig. 4.12). The simulated single-ended output voltage of the chip input chain is illustrated in Fig. 4.13 showing that, with the expected input power, the PLL output is almost at its 1V rail. 128 45µm Psub DNW N+ Figure 4.9: Photodiode layout. Figure 4.10: Input chain schematics (Fig. courtesy of C. Ives) PLL design As mentioned before, a low multiplication ratio PLL allows to synthesize a signal with a large bandwidth and low integrated jitter. The PLL loop filter bandwidth should not be more than 1/10, preferably 1/20 of the reference frequency [108]. In contrast, a small PLL bandwidth will better reject the input reference noise that is introduced by the TIA-LNA. Here we implement a PLL with a loop bandwidth of 50MHz as a tradeoff between the two. The PLL block level is illustrated in Fig. 4.14. Due to the high output frequency, the first division is done with an injection locked frequency divider (ILFD). Subsequent stages are a CML divider and a TSPC divider, as illustrated in Fig. 4.15. The control voltage of the ILFD is connected to the PLL control voltage in order to increase its lock range. It is matched to the VCO’s frequency tuning as shown in Fig. 4.17. After that, a current-mode logic 129 Figure 4.11: PD LNA with a gain-boost −𝑔𝑚 cell (Fig. courtesy of C. Ives). 130 Figure 4.12: A common-mode stabilized inverter amplifier (Fig. courtesy of C. Ives). Figure 4.13: Transient simulation of the input chain’s output (Fig. courtesy of C. Ives). VCO REFin 28GHz CP PD R C C R2R DAC C 3.5GHz ÷2 TSPC REFout R 7GHz ÷2 CML 14GHz ILFD Figure 4.14: An ×8, 3.5 GHz to 28 GHz PLL schematic D-FF D-FF VDD VDD VVCO (a) R VDD R ILFD 131 VDD VVCO VDD Vc Vout,n Vout,p (a) R Vc Vout,n VDD R Vout,p (b) Figure 4.15: VCO and ILFD schematics. (CML) and a true single-phase clock (TSPC) dividers, as shown in Fig. 4.16 are sufficiently fast. The PLL estimated noise and loop stability are shown in Fig. 4.18, demonstrating estimated performance on-par with current state-of-the-art. Tx chain design The Tx output chains consist of a vector modulator phase-shifter and an output PA. Fig. 4.19 shows a simplified vector modulator schematics. The polyphase filter used is single stage RC filter [109] since its loss is sufficiently low and its bandwidth is sufficiently large. The vector modulator provides sufficient gain and output swing to drive the PA and is designed to provide a 6-bit phase steering accuracy. Fig 4.19 shows the achievable phase shift on a constant gain circle. The power amplifier is an overdriven linear amplifier with a series inductance added at the drain of the output stage to better align its voltage and current waveforms. While more sophisticated topologies exist [110], this amplifier is robust with a reasonable output power and drain efficincy (12.5dBm and 28%, respectively), and allows to be operated at backoff should we want to demonstrate a nonuniform phased array operation as well. Fig. 4.21 illustrates the power amplifier schematics and Fig. 4.22 shows the simulated output swing and small signal gain. (b) Vout,n 3.5GHz ÷2 TSPC 7GHz ÷2 CML 14GHz 132 ILFD D-FF D-FF VDD VVCO (a) R Vc VDD R Vout,p ,n Vout,n Vout,p VDD (b) (b) (c) Figure 4.16: PLL intermediate and last stage divide-by-2 circuits. (a) A general structure of a differential frequency divider, (b) CML logic for 14 GHz to 7 GHz division, and (c) TSPC logic for 7 GHz to 3.5 GHz division. Figure 4.17: PLL ILFD lock range alignment with the VCO control voltage. 133 (a) Vout VDD Z=65Ω VCAS VDD Vin,p Ltune (b) Vin,n Ltune Figure 4.18: 28GHz PLL simulation of (a) transient VCO control voltage and (b) transient jitter. Estimated jitter is ≈ 60 fs. VDD Ltune Vin,p Vi,p Vout,n Vout,n R C Vout,p Vout,p Ctune Vq,p Vin,p Vin,n Vin,p Vc R Vin,n C Vi,n Gilbert Cell Gilbert Cell R C Vq,n R Polyphase Filtre C Vin,p Vout,n SWp SWn Vin,n Figure 4.19: Output channel vector modulator phase shifter schematic. Vout,p 134 (b) (a) Figure 4.20: Vector modulator phase shifter. (a) Small signal gain and (b) transient phase shift simulations. Vout VDD Z=65Ω VCAS VDD Vin,p Ltune Ltune Vin,n Figure 4.21: Power amplifier output schematic. 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