Packet-Switched On-Chip FPGA Overlay Networks

Author: Kapre, Nachiket Ganesh

Year: 2006

Degree: Master's thesis

Advisor: DeHon, Andre

Committee Member: Unknown, Unknown

Option: Computer Science

DOI: 10.7907/8NFZ-4Y29

Abstract

As we scale to larger chip capacities, it becomes possible to map large, concurrent applications to programmable fabrics. These applications often have irregular and dynamic communication requirements. Packet-switched networks provide efficient implementations for such applications on these fabrics. In this research, we show how to engineer high-performance packet-switched on-chip networks and provide quantitative comparisons between different kinds of these networks. We analyse different network topologies and justify selection of topologies based on experimental results. We investigate packet-switched and time-multiplexed styles of routing and provide guidance on which style is appropriate for which application.

Files

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