The Application of Tunnel Diodes to Switching and Logical Circuits Citation O'Regan, Patrick Gerard (1964) The Application of Tunnel Diodes to Switching and Logical Circuits. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/ZPA2-X230. https://resolver.caltech.edu/CaltechETD:etd-10222002-085219 Abstract No abstract submitted. Item Type: Thesis (Dissertation (Ph.D.)) Subject Keywords: (Electrical Engineering) Degree Grantor: California Institute of Technology Division: Engineering and Applied Science Major Option: Electrical Engineering Thesis Availability: Public (worldwide access) Research Advisor(s): McCann, Gilbert Donald Thesis Committee: Unknown, Unknown Defense Date: 1 January 1964 Record Number: CaltechETD:etd-10222002-085219 Persistent URL: https://resolver.caltech.edu/CaltechETD:etd-10222002-085219 DOI: 10.7907/ZPA2-X230 Default Usage Policy: No commercial reproduction, distribution, display or performance rights in this work are provided. ID Code: 4200 Collection: CaltechTHESIS Deposited By: Imported from ETD-db Deposited On: 22 Oct 2002 Last Modified: 20 Jan 2024 00:09 Thesis Files Preview PDF (O'Regan_pg_1964.pdf) - Final Version See Usage Policy. 8MB Repository Staff Only: item control page

THE APPLICATION OF TUNNEL DIODES TO SWITCHING AND LOGICAL CIRCUITS Thesis by Patrick Gerard O'Regan In Partial Fulfillment of the Requirements For the Degree of Doctor of Philosophy California Institute of Technology Pasadena, California 1964 ACKNOWLEDGEMENT The author wishes to express his gratitude to his advisor, Dr. Gilbert D. Mc Cann, for his help and guidance in the formation of this thesis. Sincere thanks are also due to those who assisted in the preparation of the manuscript. Part of this work was done for the Office of Naval Research under contract Nonr 220 {39), TABLE OF CONTENTS 1. The Equivalent Circuit 2. Tunnel Diode Switching Circuits Basic Considerations The Switching Times Multiple Inputs and Diode Tolerance, OR, AND, and COMPLEMENT Circuits 3. The Connection of the Logical Elements Passive Network Coupling Directional Coupling Using Blocking Diodes Synchronize Coupling Techniques 4, Miniature Electrical Delay Lines 5. Registers and Memory Elements 6. Summary and Conclusions Partial Table of Symbols References Appendix i Page ll 15 26 62 62 62 67 105 130 137 140 143 144 Page ] PART | In this thesis the tunnel diode is considered as an active device having an equivalent electrical circuit of figure 1.1. Even though this equivalence has been accepted for some time now some simple tests were made and comparisons between theoretical and experimental results are in good agreement, The theoretical results were obtained by integration of the non linear differential equations, The Burroughs 220 computer was employed anda special compiler was developed to simplify the analysis. The compiler was also used for subsequent analysis which was often resorted to when the construction of the circuits became a difficult and time consuming task. It can be employed for any planar, and many non planar, tunnel diode circuits and a complete description is given in Appendix l. Measurement of Parameters The techniques employed to measure the four parameters of figure 1.1 were: 1) Ry the equivalent series resistance, is determined by back biasing the diode heavily and measuring the slope of the V-I characteristic. While this may not be a very accurate method it does put an upper bound on the value of Re In the great majority of cases R, was so small that it could have little effect on the performance of the diode as a circuit element, (1) As an example the value of Rs for an experimental germanium diode produced by Bell Laboratories (GO 1032 -- peak current 10 mA) was Z ohms. 2) R, the equivalent nonlinear resistance is obtained from the V-I characteristic. In the negative resistance range the diode must be stabilized and the conventional method of shunt resistance and compensation for the shunt resistance current was employed. 3) L. and C, the equivalent series inductance and shunt capacity, were determined by calculation from slotted line measurements, L, and C were found to be independent of frequency. Page 2 The capacity C closely followed the analytical expression Cc = Co (1.1) A} 1 - (V/V) where Co V and Ve are the capacity at zero bias, the diode voit- age and the energy gap of the intrinsic material respectively. (e.g. Ve = 720 mV for germanium) Figures 1.2, and 1.3 and 1.4 show experimental results for the variation of C with V for three diodes together with the corresponding theoretical values derived from equation 1,1. The values of Ly obtained were rarely greater than 2myuHenries. A Switching Experiment The behavior of the diode under switching conditions was examined experimentally for correlation with predicted behavior, A first attempt using a step input as the driving function was abandoned because the diode switched so rapidly that the sampling scope's rise time limitations obscured the diode's true behavior, A more meaningful test was finally performed in which the diode was driven by a ramp input and permitted to oscillate during the transient response. The frequency and amplitude of the oscillations are directly related to the diode parameters, The test circuit is shown schematically in figure 1. 5 which can be reduced to the equivalent circuit of figure 1.6. In figure 1. 6 Re it Thevenin equivalent resistance of the test circuit = 40.18 ohms (measured). C WW Lumped parasitic capacity of the test circuit = 10 pF (estimated). The value of C. had essentially no effect on the analytic solution over an extremely wide range of values tt UI Lumped parasitic inductance of the test circuit = 5 - &mpH. Lat Lumped parasitic inductance of the diode mount = 2 my H. Page 3 Ry and Ch = An approximation to the scope delay. Ry = 800 ohms Cy = 0.5 pf. (Load on circuit negligible). The diode (V-I characteristic on figure l. 7) was represented by its equivalent circuit and the diode capacity was assumed constant at 2.5 pf. A comparison of experimental and analytical results is shown on figure 1. 8 and clearly good agreement was obtained. The deviation at the higher values of the voltage was attributed to the in- crease in the diode capacity (equation 1, 1). Even though the diode capacity is voltage dependent (figure 1. 4) for the analysis it was assumed constant and equal to the valley capacity. The compiler operates on this assumption and since the diode voltage will rarely exceed this value by more than 50 mV the rise and fall times of the diode will be overestimated thus guaranteeing an error (if any) on the conservative side and making a certain allowance for diode to diode variation of the capacity. Other results given in the following sections of this thesis will provide further support for the validity of the equivalent circuit. Page 4 Figure L.l:- The equivalent circuit of the tunnel diode Page 5 aporq eye syroumsjeny seKay - eBeiyoA ‘sa aauvqysedey -!2 'T arnt ir Aw 0OOT 008 009 00F 002 é Cae yTernsi0ceyy ——— feweutzsdxy o r OT (td) saueqpoede 00s 96rz 2porp umraeuTeEN GH - asesjoA “8A aouviede «tg ‘7 aanaty Aut 00F O0€ 002 oot 0 i. 7” Li ae Page 6 TeIWeI10Eeq], —— Teyueuryzodxy O r 6OT ral (qd) aauezpoede 00P oo€ ZE0l OD ed - eBewo, “sa soueqeded -'p ‘T ornd1 7 Aw 002 Oot 0 2 r qespeszoaqy, ——— Tewoutredxy © (qd) asweqpeden Page 8 nl Step 4 10 db Inte- Test 20 db Sampl source atten- grator diode atten- | acope uator uator Figure 1.5:- Test circuit for a ramp input Cy Looe ao) L Re Ramp Saeed Cy, generator Test diode Figure l.6:- The electrical equivalent of figure 1.5 Current (mA) Page 9 0 © ©:100.~—200 300 400 500 606 Voltage (mV) Figure l.7:= V-+l Characteristic of Bell GOl032 Page 10 500+ 4001 >. a _@ 300F 4 > oy % 2004 8 o Experimental —_ Theoretical 100 F 0 1 ra 3 . & 5 Time (ns) Figure 1.8:- Bell GO 1032 response to a ramp input Page ll PART 2 TUNNEL DIODE SWITCHING CIRCUITS (A) Basic Considerations Consider a tunnel diode in series with a linear impedance Z(s) and driven by an ideal voltage generator as shown in figure 2.1. Suppose now that Z(0) = R. Static load lines can be drawn for different values of R and for different values of the supply voltage E (considered asa D.C. supply). These will usually result in either one or three points of intersection with the diode characteristic, At any voltage between the peak and valley voltages of the T. D. the dynamic diode resistance Rp is negative. Let Rmin be the minimum value of /Rp/ in this range, Clearly if R < Rmin only one point of intersection is obtained which may be stable as in (2) and (2B) of figure 2.3. (The stability or instability in case (2A) cannot be deter- mined from static considerations.) If R > Rmin there will be one stable intersection point as in (1A) and (1B) of figure 2.2 or two stable and one unstable point as in (1) of figure 2. 2. Following a disturbance the locus of the diode current can be plotted against the capacitor voltage by sulving the non-linear differential equations. This locus will be called the dynamic trajectory. Much information can be obtained about this trajectory without directly solving the differential equations if Z(s) has a simple form. Suppose Z(s) = R + L_ Sas shown on figure 2.4 and let the disturbance be introduced in the form of a step increase in E from Eq to E, as shown on figure 2.5, With this step increase in E the current and the voltage of the dynamic trajectory increase from their initial values (Point N) to those at Q. Once Qis reached the voltage will continue to increase but the current will decrease monotonically until Ris reached. After- wards the current and voltage will approximately follow the diode characteristic towards S, Page 12 For any point A on the dynamic trajectory between N and § the fullowing equations can be written. dv I- T — - —7F (2.1) dt Cc dl Vi -~ V we (2.2) dt L + L m s Equations 2.1 and 2.2 are the parametic equations of the dynamic trajectory. AtN, RandsS dv = 0 but-atS at is also zero, dt. dat Accordingly at N and R the dynamic trajectory has an infinite slope but the same is not usually true at S. The current is a maximum at Q and from equation 2. 2 once the trajectory passes through the load line (at Q) the current will always exceed the load line current for any value of the voltage. The dynamic trajectory has associated with it, a third variable, namely time. Let (V, I, t) be any point on this trajectory. At time t the output voltage (i.e. that between A and B in figure 2.4)is given by the equation Vout = V + RoI + AV (2. 3) Lo+L where AV=E-(R+R)1I-V (2,4) Note that AV is the horizontal distance between the dynamic trajectory and:the load line (AV = V, - Von figure 2.5) and is accord- ingly divided between the inductors L and L. in proportion to their magnitudes. Note also the AV has a positive maximum at:N (figure 2,4) is zero at Q:and. is negative between Q and R. A diode, whose parameters.and characteristics are given in figure 2.6 in series with a 34 ohm resistor and an inductor Lo and Page 13 operating at the point N (see figure 2, 6) has its driving voltage E in- creased att = 1 from 700 to 800 mv. Some computed dynamic trajectories and their corresponding output voltages are shown on figures 2.7 and 2.8 respectively, The output voltage has the peculiar property of decreasing after the initial positive output step (output step iS equal to < that of the input). The explanation lies in the fact that AV ——————. at iirst decreases more rapidly than V + Ro in~ Lo + L. creases (see equation 2.3), Mathematically it can be shown that L dVout dv s dl = — +R 1 - - R{— dt a s) ( Lin + Le ) |g L n s dE (2.5) Littl, a For t>0 22-0 50 —— will have opposite sign to = unless dt av. ar” R (1 + L/L) - R, (2. 6) Si dv. . : . ince ar is the reciprocal of the slope of the dynamic trajectory at t = 0, av = 0 and since ar - AV > 0, dVout is negative dI dt L+ iL dt s (R >> R,) and will remain negative until equation 2.6 is satisfied by equality, Suppose that equation 2.6 is satisfied by equality at time f i.e. that Vout (€) is a minimum point. The two important characteristics of the "oscillation" are:- 1. The amplitude of the "oscillation" A. (A = Vout (0 +) - Vout (f)y* Nw The time it takes the output voltage to reach a minimum (i.e. the time f). * See figure 2.8 Page 14 For values of R >> Rmin the minimum output voltage will occur at a point very close to point Q (figure 2.5) of the dynamic trajectory. Calling AE the input step for R >> Rmin L A = ——=— AE L +L m s and t will, for a given AE and values of the diode parameters except Ly: depend on the sum of the inductors Lo and L.- Conse - quently for values of R >> Rmin anda step input it should be possible to match theory and experiment to determine the values of the inductors L andL.. m s However, when R is not sa large the minimim value of volt- age deviates considerably from that of Q (figure 2.5) and depends on the dynamic trajectory and hence on the sum of the inductors as well as on their ratio (equation 2.6). The time t will then depend on the ratio of the inductors as well as on their sum. Furthermore if the input step has a rise time the amplitude of the oscillation (A) will be reduced by a factor depending on the sum of the inductors. Since in practise the input step must have a rise time and from bias voltage and gain considerations R should not be greater than 4 or 5 times Rmin the values of Lin and L, will in most cases be indeterminate from the amplitude of the oscillation and the time f. Indeed in most cases the circuit parameters will be such that there will be no such oscillation in the output pulse. To illustrate the occurrence of such an oscillation in practise an experiment was set up where Z(s) (figure 2.1) was a purely resis- tive delay line and L. could be artificially increased. The circuit and diode mount are shown in figures 2.9 and 2.10. The extent to which L, is incremented depends on x and d (figure 2.10) and output pulses for different values of the effective value of L, are shown on figure 2Z, ll. AZOmAR.C, A. stripline tunnel diode was used with zero d.c. bias, Page 15 (B) The Switching Time 1. The Effect of the Load Line and the Percentage Bias. If inductance and stray capacitance are negligible the dynamic trajectory follows the load line as is illustrated in figure 2.12 for a switch from the low to the high state when the driving vollage experiences a step increase from E, to E, att=0. Atany 0 1 point (V, I, t) on the dynamic trajectory the equation ste st. le of +e 4, is valid where I, is dependent on V as shawn on figure 2.12. Conse- quently the time (t)_>) required for the voltage to increase from V1 to Vo is Vv 2 dv t =C _— (2. 6a) 1-2 D In general the selected values of vy and V5 will depend on the application of the switch. Vy and V5 might for instance be the 10 and 90% points if the switch is used as a pulse generator, However in logical circuits the initial delay (0 to 10% say) is also important and numerically we shall consider only the 0 to 90% time. . (i.e. figure 2.12 Vy = Vn and V5 = Vn + 0.9 (Vis - Vy) Strictly speaking we shall consider the 0 to 90% rise time of the diode capacitor voltage but since R. is much less than Ry, this will be very close to U fo JU rise of the output voltage. ** Other symbols appearing later in the text (some illustrated in figure 2.12) are defined in the ''Partial Table of Symbols" (Pages 140-142). Page 16 Equation 2fa can be written in the form y Cp a av 1-2 = y @ Tt) Pp 1 c p Vv e t I 2 i 1-2 4p _ av 2.7) C (I /1 D Vv, c p) Since the characteristics of a given type of tunnel diodes (e.g. germanium diodes) can be expressed in the form IT=I1 f£(V P (V) where f (V) is independent of I, the integral on the right of equation 2. 7 is independent of I_ and for fixed limits depends only on Eo: E, and the % bias. (See footnote on Page 17) 1 Defining the parameter 7 by the equation V2 7 * | (I a ) (2-8) Vn c/*p where Vz = 0.9 V;,, +O0.1Vi the zero to 90% rise time (t) then is t-oq & (2.9) I p Also from equation 2.8 and figure 2,12 it is easily seen that rt =f (Ep, E,, % Bias). Furthermore if the gain G is defined by the equation Vig 7 Vay E, - Ey Ge (2.10) Page 17 then 0.9 V..+0.1V 1 = $ (Eq, G, %Bias) = H N_dV (2.1) N By performing the integration 7 can be evaluated for various x values of the % Bias, Eg and G. The percentage bias and Eo deter- mine the load line since E, - V 0 N _ Ry, =——— = RL +R (2. lla) In where R and R_ are the external load and the series resistance of the diode respectively. Viz can then be determined graphically or analyt- ically and then c re or V..- Vv I/l = (e+ LN _ yy - ev) cP TR 0 G p L 1. e. I 1 Vi.- Vv 1/1, == ———— (©, + 4+ _¥ - v)- iy) (2, 12) >» =o - YN G By dividing the V axis into a number of intervals and approx- imating f (V) in each interval by a quadratic or linear function of V the intergration of equation (2.11) can be performed analytically. Using four regions as illustrated in figure 2.13, a very good approx- imation to f (V) is obtained in the range of interest. Using the notation of figure 2.13 it will be assumed that £(V) has the form * The % Bias is defined as 100 Iy/t, where ly and I, are the bias current and tunnel diode peak current respectively. Page 18 2 1 (a, + b (V- Vv.) , vy, s Ve Vy . 1 L + m (V, - V) : vy < Vi< V5 £(V) =< (2.13) ap + by (V -v,)° , Vv, < Vs Vy la, + db, (V - V.) ; Vv, < V < Vy where 1-1 L.-1 a,=l a, =a,=1, b= - — m =———, 1 3 y’ a i (V_- V,) V5-V) I, - Iv I, - I (V_-V5) (V_-V3) The integration of (11) then gives 1 - 1 Vy 7 Vu 7 %21 T = log. . by (a)-@)) Vv - a Vu > 1 21 V. + B/A + —_ log é A © 1 Vy + B/A Ve-e V - @ + 1 log, v 12 2 22 bo (a 9-45) Vi - %22 Vo - %42 1 Ve 7 3 V7 %23 | (2,13a) + log. ——ow b3(a)3-%3) Ve %3 V7 %3 Page 19 I B= __N (GE G(E,-Vy) nN? ot Ya 7 V and Ve = 0, IVs + 0.1Vi if Ve > Vv If Ve < vy then the 4th term in equation 2.13 is omitted and in the 3rd term of the same equation Vy is replaced by Vee Finally Vay is determined from the expression . I I 2 I EI Vin 2 V,- —N fry ED iv, O'N (2.14) 25i(EQ7 Vy) 24 EQ- VN) b, b(E,-Vy) In equation 2, 14 if Viz3 > Vi, then V,, = Viz but if Viz3 < V, then Voz = The values of 7 as given by equation 2.13a were evaluated for a germanium diode whose V - I characteristic was approximated by equation 2.13 with the parameter values given in figure 2,13, The computation was performed on the Burroughs 220 computer for three different values of the % bias (92.5, 95 and 97. 5%) and the results are plotted on figures 2, l4a, 2.14b,. and 2.14c. These results quantatively express the dependence of 7 on Ey and the percentage bias. They show that the minimum value of 7 is obtained with a unique value of E, when the % bias and gain G are fixed. This value of 7 and the cor- responding value of Ey can be read or interpolated from figures 14 when the gain G and % bias are known. As an example the minimum value of 7 is 1.5 my secs/pF/ mA when G = 6 and 95% bias is employ- ed. This minimum value of + occurs when E, = 500 mV and using this result in conjunction with equation 2.9 the minimum zero to 90% rise time for a 20 mA, 10 pF tunnel diode with a gain of 6 and 95% bias is equal tol,5 10 = 0,75 my secs. 20 . On figure 2,12 as Ey decreases and consequently as G increases the value of + increases and eventually approaches infinity Page 20 when the dynamic trajectory becomes tangent to the diode characteristic. The value of G corresponding to this infinite value of 7 will be called Gmax and it is dependent on the percentage bias and EQ: The results of figures 2.14 can be applied to any single diode circuit with linear resistive elements. Using Thevenin's thearem the circuits of figure 2, 15a and b are equivalent if 2-4L;4;44 (2, 16a) R Ro Ry Ry and (R,R_) / (R, + R_) (R,R.,) / (R, + R,) E, = Ey ames) 2 2 +E Mm 1 2 (2.15) R, + (RAR MR, +R) Ro + (RyRo)/(Ry +R) so that an input step AE,in Ey corresponds to an input step AE. (RAR I)/(Ry + Ry) / [Ry(R,R,) / (Ry + RA)] AE, = in E, if E is maintained constant. Accordingly calling c} the gain in figure 2.15a this is related to the gain G of equation 2.10 and of figures 2.14 by the equality cl _ AE, : R5R, / (Ry + R,) G AE, Ryt(R,R,) / (R, + R,) or R G = _s ci (2.16) R € where R is given by equation 2.16a. Also from equation 2.15 i} &<=9 R . E=-—2 E, (2.17) R and from equation 2. lla EB, =(R+R ly + Vy (2.18) Page 21 Example: .Suppose it is necessary to design the circuit of figure 2,15a to have a gain (G1) of 3 at 95% bias and have a minimum zero to 90% rise time for this gain when using a 20 mA tunnel diode with a load (R5) of 50 ohms anda D,C. supply voltage E of 5 volts. A easy approach is to start by assuming Eo and from figure 14h if Fy = 500 mV 7 should be close to its minimum for all possible values of G. Using this value of Ey equation 2.17 gives 5000 10 and equation 2,18 then becomes 500 = (R+ Roly + VN = (R + 1)19 + 48,7 Accordingly R = 22,8 ohms and Ro = 228 ohms Then from equation 2, l6a R, = 41.7 and from equation 2,16 G=5.5, Therefore the assumption that Eo = 500 mV is good (see figure 2.14b) and 7 = 1.375 mys/pF/mA. If the tunnel diode has a capacity of 10 pF then the minimum zero to 90% rise time for a gain of 3is 7 C/I, = 1,375 sy + 0.7 my secs, From equation 2. l6éa R, > Rand then from equation 2.16 G> ch Clearly from these equations for a given value of c} it is necessary to make Ro as large as possible to minimize G and accordingly r for a given load resistor R, i.e, the d.c. supply should be a current source. Equations 2.15 through 2.18 are transcendental since the optimum value of Eo is a function of G but * ‘Tunnel diode of figure 2.6 Page 22 on the other hand this optimum value is only weakly dependent on G so that not many trials have to be made (in the previous example the first trial was successful) if a reasonable value of Ey is first sclected. This method of analysis will be later employed in connection with multiple inputs, fan out ratios and diode tolerances. However the effects of series inductance will be now investigated. z. ‘Parasitic Series Inductance. Equations 2.1 and 2,2 when combined give I-I (L +L) ‘ m s dV = d dl Cc Vy - V 1.¢e. LI dV =P iyi - vy} / [E, - RI- Vv] (2.19) dl Cc Pp where L =L, +t L,. Since 1/1, and RI are independent of - the effect of series inductance on the dynamic trajectory and accordingly on the zero to 90% rise time parameter 7 is from 2,19 dependent on the product LI/c and on Eo: Figure 2.16 shows the dependence of 7 on the gain 0 {500 mv) and for various values of the parameter LI,/C where Lis measured in mu H, T inmA and Cin pF. On the other hand figure 2.17 shows the dependence of 7 on Eo for a fixed gain (4) the same % bias (95%) for G for fixed values of the percentage bias (95%) and E the same values of the parameter LI/C. These results were obtained using the circuit analyser and the same approximation to the tunnel diode characteristic as in part (1) of this section. The results clearly indicate that the zero value of LI _/C does not always give the fastest zero to 90% rise across the diode capacitator. However as figure 2,8 shows the effect of inductance is to produce overshoot and a large increase in recovery time so that Page 23 the maximum repetition rate will invariably be obtained with zero or extremely low values of LI /C when some type of a reset pulse is employed. | Consequently the d.c. power line and especially the input resistor should be as noninductive as possible. The output resistor should be also of low inductance to supply a sharp input pulse to the next stage. This naturally leads to the idea of input and output trans- mission lines (figure 2.18 with r = 0), A transmission line input has the added advantage that the gain ci is halved with a consequent decrease in 7 and the characteristic impedance is almost entirely resistive. However, due to reflection problems it may be necessary to insert a resistance in series with the input line as in figure 2.18 and then while the gain c is still halved the input impedance is now the sum of the characteristic impedance ofthe line and this resistor. 3. The Impedance Level. Since the parameter 7 is independent. of the impedance level the rise time can be minimized by selecting the tunnel diode with the maximum value of r/c providing the value of LI_/C is not too large. Of the tunnel diodes presently available the quantity r/c increases with I, and since their series inductance (L.) is low (about 0.4 myH) and could be further decreased by direct deposition, faster switching occurs with higher value of I,’ The only limit is that imposed by power considerations the latter being proportional to I: 4. A.C. Bias. Using A.C. superimposed on the D.C. bias the switches can be synchronized and the A.C. can also act as the reset pulse ina return to zero circuit, The single diode circuit will be considered as operating in this way. If the driving voltage E, is replaced by E where E = (E 0 e,) + e Sinwt then the maximum value of E would give about the same % bias as the D. C. voltage Eo: Page 24 The load line would than vary with time between the limits shown on figure 2.19. Due to time variation of the input and E switching will occur under the influence of a varying load line. The parameter 7 in addition to its dependence on the % bias, the Gain and Eq is now also dependent on w and the amplitude of the A.C. clock. Ifw is sufficiently low the switch will be completed with a virtually static load line. Asw or the A.C. amplitude increases the load line will drop more and more during the rise time of the diode which leads to incomplete switching and eventually to complete suppression of the output. The analytical solution of this problem now becomes extreme- ly difficult so that it is necessary to resort to a qualitative discussion and experimental justification. ~ Basically the A. C. amplitude must be kept as low as possible to minimize its effect on the rise time but at the same time sufficiently large to guarantee the reset. An inspect- ion of figures 2.6 and 2.14 indicates that the maximum value of the bias should be about 500 mv and an A. C. peak to peak amplitude of 300 mv should be sufficient to guarantee reset. Denoting the clock period by T, the origin of time when the clock reaches its peak, and using an input that is some fraction of the output then except for mar- ginal cases which must at all times be avoided switching will be initiated at a slightly negative time if the input reaches its maximum value att = 0. Since switching should be completed before the A.C, component of the bias goes through zero the zero to 90% rise time cannot be greater than T/4, With these restrictions the rise time should be fairly close to that predicted by the parameter 7 and the * This problem is further discussed in Chapter 3 in the section titled "A, C, Bias Amplitude." Page 25 maximum operating frequency would approximately be f - tL (2. 20) max 47 C/l T i, An experiment shown schematically on figure 2.20 was set up to justify these statements. A 20 mA tunnel diode (lOpf) which was essentially operating into a 25-ohm load was used. The peak A, C. bias was 150 mv and the D.C. was about 350 mv the latter being adjusted to give 95%bias. The trigger was also supplied by the A. C. generator the amplitude of the trigger being the excess over that necessary to give bias amplitude. The gain was computed from the ratio of the output amplitude to the trigger amplitude and the measured marginal gain at 300 megacyles was about 7.5 which is in reasonable agreement with the theoretical figure of 8 on figure 2.14b. Some oscillographs of the results obtained are shown in figure 2.20b. In these oscillographs the lower trace is a marker indicating the clock and input phase, The experimental values of 7 are compared with their theoretical counterparts in Table 2.1 and good agreement is evident. TABLE 2.1 300 Megacycle Clock Input. Output T T Amplitude Amplitude Gain Experimental (Theoretical) 55 380 7 1.8 1.9 76 400 5,25 1.4 1.3 100 420. 4,2 1,2 11 125 430 3.4 1.0 0.9 Page 26 Hence, .even though the 7 parameter is slightly artificial when A. C. bias ic employed it can be uscd as a useful guide to design and equation 2.20 will supply a good approximation to the maximum operating frequency. (C) Multiple Inputs and Diode Tolerance, OR, AND and Compliment Circuits Here the effect of parasitic inductance and capacity will be again neglected except for a few qualitative comments. Defining the parallel impedance of all the output impedances as equal to R, then for Ro >> R the parallel impedance of all the inputs is RF where RR, R, 2 (2, 21) R, -R and from equation 2.18 R = (Ey-Vy)/Iy- R (2. 21a) s Suppose the input and output circuits are transmission lines and for the time being let us eliminate reflection problems by using sufficiently long lines. Then if the parallel impedance of the input lines in the high voltage state is R (R3 > Rj) and Gi is defined by the equation c} = output line voltage/input line voltage corresponding to equation 2.15 we now have G = As ci (2,22) ZR where the 2 in the denominator results from the fact that the equiv- alent input circuit for the transmission line is a voltage source of twice the transmission line voltage with an output impedance equal to the characteristic impedance of the line as is illustrated in figure 2.18. The input line voltage will in general be some fraction of the output voltage of a similar circuit and so Gc} will be known, Then depending on the value of R,/R the gain G will be > Gmax in which case the diode Page 27 will not switch or < Gmax in which case it will switch if the correct value of Eo is used, The value of Gmax maximized with respect to Eo is the 7 = curve on figure 2.21, Due to diode tolerance this Gmax varies between some limits for any % bias. In tunnel diode circuits where the diodes are biased near the peak current the most important diode tolerance is the percentage variation of this peak current and to a high degree of accuracy this % tolerance is equivalent to a similar variation in the % bias. This will result in upper and lower limits in the above value of Gmax which we shall call Gy and Gy (G., > G,). Then for values of G>G,; the diode will not switch, for G < Gy the diode will switch and if Gy <G< Gry the outcome is indeterminate. Example: Suppose the nominal bias is 95% and the peak current variation is guaranteed between 11% Then from figure 2. 21 Gy = 10.6 and G) = 7.7 In general Gy and Gy depend on the percentage bias and diode tolerance and we must be careful to select R3 so that G does not ever fall in the indeterminate region (G) <G< Gry) to insure logical operation of circuit. Keeping this in mind together with the fact that as low a value of the parameter 7 as possible is desired some logical circuits will now be considered. 1) The Logical OR Circuit. Consider a logical OR circuit with n inputs and m outputs all of the same characteristic impedance. When i of the inputs are high equation 2.22 becomes G = mt. gi | (2, 23) 2 2i Since the maximum value of G; occurs for i = 1 the only requirements are that 1 > G <G (2. 24) Page 28 and that the bias % plus the % tolerance of the peak current will be less than 100. In practise a certain allowance should be made for circuit noise, drift in the power supplies, etc., the net effect being to lower G._. L All the tolerances including that of the diode peak current tolerance will result in a fixed tolerance in the %bias. Let this tolerance be 1t6% <A practical method of approach consists of putting an upper limit in the permissible value of 7 and then making an allowance for &. If this upper limit of + is 7max then equation (2.24) becomes G, = G <G (2, 24a) where Gis the gain at + = 7 . For any value of + the _ max max value of G can be plotted against the % bias by means of a crossplot from figure 2.14,If on this crossplot G = X when the % bias is Y then to guarantee G < G the percentage bias must be equal to Y + 6, In addition Y + 26 must be less than 100%, The maximum operating frequency fmax as given by equation 2.20 now becomes f = (2. 20a) so that higher values of T max lead to lower values of fax’ On the other hand higher values of T max will lead to higher values of the gain and by equation 2, 24a to higher values of m and n. An inspection of figures 2.14 shows that very little additional gain can be achieved for values of + > 2. Consequently this value of 7 will give the approximate upper limit of the sum of the fan in and fan out integers m+n, : On figure 2.21 the curve marked 7 = 2 is the plot of G against the % bias for 7 = 2, Using this plot and proceeding as max outlined above Table 2.2 was constructed. It shows the maximum Page 29 permissible values of the % bias and the corresponding minimum values of the gain G for various values of the percentage bias tolerance 6, TABLE 2.2 5 Maximum % Bias Minimum G for rt < 2 1 99 12,2 2 98 8.2 3 97 6,2 4 96 5.2 5 95 4 With the tunnel diodes presently available the minimum practical value of 6 is about 1.5. Hence a value of G of about 10 is attainable. In part 3 it will be shown that the minimum value of ci is 2 so from equation 2, 24 the maximum value of sum of the fan in and fan out integers is about 10. It will be also shown that due to power supply consideration this number must be slightly reduced so that the upper limit of m + nis 8 or 9. From the above considerations the simple tunnel diode circuit will operate effectively as an OR gate and the sum of the fan in and fan out integers can at least be as high as 8. This brings the OR gate well within the range of practical application. 2) The Logical AND Gate. Equation 2,23 is also applicable to the AND gate where i is the number of high inputs, Since the circuit must switch for i=n and must not switch for i = n-1 equation 2, 23 gives Page 30 and (2, 25) mtn ci > Guy 2(n-1) one consequence of the relations 2, 25 is that G = nel G 2 , (2, 26) n-~l Gy, From equation 2,26 it is easily seen by inspecting figure 2.21 that, for a given %tolerance in the peak current, asn increases the nominal % bias must decrease. Example: For a peak current tolerance of =11/2% we obtain Table 2.3 where some of the values of ¢ nominal and 7 max TABLE 2. 3 Yo Bias Gy Gry “max a G Trominat) Vmax. 97,5 10,5 25 1 - - - - 95 6.2 11.9 2 2 6.0 1.5 2.4 92.5 5,5 7.7 3 3 5,2 1.8 2.2 92.5 5.5 7.7 3 2 3.9 1,15 1, 25 were obtained by interpolation from figures 2.14, Even at 95% bias the maximum permissible value of n is only two and the spread in the value of 7 due to diode tolerance is about 100% of the nominal value. Also a value of c} of 6 is so high that the noise level would have to be very low. On the other hand at 92.5% bias andn = 2 a lower value of 7 is possible with much less % variation but c is probably still a little too high. The solution then is to retreat to lower values of the % bias and this is justified diagrammatically for n = 2 in figure 2. 22, Page 31 There are however, many objections to this approach: a) The inductive effect may lead to false switching as is illustrated if figure 2.23 for n = 3 where for 2 inputs high the inductance causes the dynamic trajectory to deviate sufficiently from the load line to cause the circuit to switch if the diode peak current was less than its nominal value. b) If we use a A.C, bias superimposed on D. C. where the A.C, acts as a synchronizing and reset clock then the load line and the input pulse will be time variant. Presumably the clock and input should reach their peak values at abuut the same time to initiate switching and then the load line will fall off as the input and A.C. bias decrease. The lower the % bias the more dependent the load line becomes on the input signal and the greater the tendency towards incomplete switching. Accordingly tunnel diode circuits reducible by the Thevinin theorem to that of figure2.tare not directly suitable as AND gates, However since OR circuits operate best at high % bias and the problem of false switching due to inductive overshoot in the neighbourhood of Vp does not apply the same circuit is suitable as an OR gate, 3) The Modified AND Circuit. Consider the circuit shown in figure 2. 24a with the negative bias E (figure 2.24b) where the circuit switches when /E/ isa maximum unless a positive pulse is applied at the input. This circuit operation is similar to that of the positively biased circuit except that the percentage bias will be (100 + 6) instead of (100 - &)%and the presence of a positive pulse at the input hinders switching instead of causing it. The output will then be the mirror image of the compli- ment of the input. For simplicity we shall designate the symbol A to the mirror image of the compliment of A. Page 32 Suppose now it is desired to construct an AND gate for the signals A, B, C, D, ---. The procedure is to generate the mirror image of the compliments of all but one of these inputs - say B, Cc: D, ---, and then apply the latters and A to an OR gate. Since the absence of one or more of the signals B, C, D, ---, will lead to a negative input to cancel the effect of A if the latter is high it is easily seen that the circuit now operates electrically like an OR circuit and is accordingly not subject to the disadvantages of the direct AND gate. 4) The Complement Circuit. The Complement of the signal can be obtained by applying its mirror image about the low d.c. bias point to an over biased OR circuit. This is illustrated diagrammatically in figure 2.25. At the frequency of interest (about 300 to 500 M'c's) it is doubtful that conventional inductive coupling could be employed in the -l1 box. An inverting circuit which can be integrated with microstrip delay lines and whose response is fairly close to -a(@< 1) is shown in figure 2.26. The conductor is insulated from the ground plane except at points A, B and C where it is connected to it. Clearly the micro- strip transmission lines are coupled to give inversion but each one is terminated in a short circuit except for the inductance introduced by the holes. A very approximate equivalent circuit is shown in figure 2.27 the capacity being mostly that across the slit of width b and breadth t as shown in figure 2.26. While it should be possible to adjust the parameters rs t and b (see figure 2. 26) to make > the d.c. short resonant at igh frequencies the analytical determina- tion of the values of these parameters as a function of the frequency is a very difficult if not impossible problem. To ascertain the applicability of this inverting device to the output pulses of a logic gate it was accordingly decided to experi- mentally determine its response to a spike shaped pulse. The experiment was set up with t = 0.2", b= 0.2"! and some selected values of ry and ry. The source spike had a base width of Page 33 approximately 1.6 my secs and the circuit is shown schematically in figure 2.28, The length of the microstrip line was 6-1/2" and (2) its characteristic impedance was 50 ohms. (Using a 10 mill teflon insulating sheet the corresponding conductor width was 32 mills.) Preliminary tests showed that the direct microstrip line and the coaxial to microstrip connectors had a negligible effect on the spike pulse but the 15 my sec coaxial delay did alter the amplitude of the spike as shown in figure 2.29a. Then the microstrip line was adapted to become an inverter as shown in figure 2. 26 and the re- sults shown in figures 2.29b, 2.29c, 2.29d, and 2.29e were obtained for the different values of vy and Yr. The inverter transmission coefficient (T) and the negative reflection coefficient (R) are shown on Table 2.4 for these various values of ry and Tr. Clearly it is not difficult to obtain up to 80% transmission which is more than adequate to serve as an input to the overbiased OR gate. TABLE 2,4 7 (inches) ro (inches) Transmission Reflection Coefficient (T) Coefficient (R) 0.5 0.5 0. 38 0. 76 1, 0 1,0 0.55 0.55 1. 8 1.8 0. 725 0,41 2.3 2.3 0, 76 0. 34 2.3. SO 0, 85 0,25 2 aed 0. 87 0.13 The reflected pulse will tend to inhibit the source from switching (assuming this is a tunnel diode) but it is possible to compensate for this effect by inserting an open circuited lossy stub Page 34 line there so that the positive reflection from this stub returns at the same time as the negative reflection from the inverter. It is also necessary to include resistance in series with the input and output lines of the inverter to control the circulating current due to the D.C. bias. Summary: A complete set of logic elements namely the OR, AND and COMPLEMENT circuits were developed. The circuits are very simple and their switching speeds are as fast as can be obtained with the tunnel diode device, Essentially the modification of the AND gate resulted in a circuit configuration most suitable to the tunnel diode device and effectively made the sensitivity of the AND gate equal to that of the OR gate. The method of analysis is independent of the diode capacity and peak current, It can also be applied for any shape of the normalized V~-I tunnel diode characteristic. However, the numerical results are only applicable to germanium tunnel diodes. The circuit design incorporates the null effect to give increas ed sensitivity and minimize the effects of parasitics, Furthermore, the parasitics themselves can be kept to very low values by means of input, output and power supply transmission lines. in Part 3 the interaction between logic elements is discussed and a method of connection is developed, A distinction between input and output lines is obtained by means of phase techniques and subject to certain restrictions the elements can be connected to perform any logical operation, Page 35 Figure 2.1 mV Figure 2,2 Figure 2,3 Figure 2.4 Figure 2.5:- The dynamic trajectory Page 37 T.D.182 Characteristics 1 1 ohm C= 10pF Ry Given by curve mA. 100° 200 300 400 500 600 700 Voltage (mV} Figure 2.6;< Vel characteristic of R. C,A.'s T. 0.182 Page 38 g9~70390fe213 Spureudp pagnduioy -:p *g eanBrz (Aur) aBe370A 00S oF o0€ 002 00t 0 ‘ lo ms r ofyetrej2Ereg> Spor “> 03 woTyeurtx0arddy —-* i ! i — ~ ae out peoy { et . ~, — ~, ~ . . “n - ~ eu 9 °O=3 —P . ~ eo ~ > ~, ~ tt ~ ~~ = tra 8 HUPp‘'O= T yu Page 39 5001 fr 400) La =O LL." enH Ls 10nH 300} > £ & 200 F 4 ) > _ loot bh i-t {L.-0) 0 -2 .4 .6 .8 1 L2 Time (ns) Figure 2.8:- Computed output waveforms Step To scope trigger source 50 ohm tee Delay line Page 40 Diede mount | Scope Figure 2.9:- Schematic layout 50 ohm line Figure 2.10:- Diode mount of figure 2.9 A AO A | Tunnel diode Pressure contact t Lo =bL = Output 5 527 bey Output Ly Le3>h,.7hby Scales:- Hor. Ins/cm. Ver. 1l00mV/cm. Figure 2.l1:- Experimental input and output waveforms of the circuit of Figure 2.9. Current (mA) Page 42 N Voltage (mV) Figure 2.12:- The dynamic trajectory when parasitic inductance is negligible Page 43 £(V) <> _~——~ Region 2 robe ' ' i j ' ! 1 «-Region 4-3 4 ' t f i re t : ‘ { ' 1 ' i to tR-+ ' } i rt ‘ j t t i t fof 4 ’ i | { Ly ro ; ' { ‘ ‘ ' ' i L i ! h = < on < ww < < < ee Voltage (mV) Typical values for germanium diodes 1 = 400, L, = 0.1; V, #45, 1) = 0.925; V., = 65; vi = 85; V9 = 150, I, 2 0.425; Vy 3 Figure 2.13;- The approximation to {(V) 0002 00ST 8019 %S 26 2” UTEB pue 9-7 UO 1 Jo VDUepuadag tac) 9a opot ops ~iepr 2? ern8z 7 Page 44 SVIG GS "26 pe , 0002 opst evtq%S6 38 UTES pure “q uo 4 yo eomepuedaq -iapt'Z S2nBTs o (At) 2 ogo! 00s a Page 45 pe 00 Si BLIG HS ‘16 72 ues pue oa Uo. FO sduepuodag (ara) Pa 0O00T 00S -iDpy 2 ornBy SV1d %S °£6 Page 47 (b) Figure 2.15 Page 48 (wm 00s)" poxty pure ayes sfqerzea soy ofr Wo 4 Jo aduapuedad ‘gy 'z aan3y a wren : “ 4 ¥ € Zz T 4 6 S oY d 02 = 9/ TT rs “tT +& ard Page 49 Ong A{QUVIxVA pue F Jo ures pax ve 207 5 [Sry uO 4. fo aduepmadsq «izt°7 9an8ry | (aw) oa 0091 o0zt 008 00% . +1 S$ 0 OT d o2 =9/° TT tT? ae Figure 2.18:- Input and output transmission lines Current Voltage Figure 2.19:- Time dependence of the load line with an A. C, bias component To scope | trigger input A. CG, Highpass Summer ° at ae oot ANG LOdb Generator Filter Attenuator dD. Cc, Lowpasa camer ene | Generator Filter To scope Page 51 Tunnel Diode Figure 2. 20a Page 52 Figure 2.20b (Part l):- Output pulse when A. C. bias component is employed. Page 53 ual | if] AG | | | | Gain = 3.4 Scales:- Hor. 0.5ns/em. Ver. 100mV/cm. Figure 2,20b (Part 2):- Output pulse when A. C. bias component is employed. 4 JO SANTA POXTy 1Oz SLIQY “BA UTED <tZ °Z ornsy 7 Page 54 seta % %S "26 %S6 %S 26 | I [ | ' | t | +s ' ' ! nee + ee > 7Or (42Z a8ed uo atdwexg cag) ‘yerand wead apotp [SUUNA aq} UT SoTeISTOPY_ pus 7 (yeupwiou) setg %¢4 207 aBuer ayen -— + ST Toe aTeED mA 2 Inputs high 1 Input high high Voltage (mV) High %Bias High ci High + High % variation in + Page 55 mA a Inputs high 1 Input high No input high Voltage (mV) Lower % Bias Lower ct Lower 7 Lower % variation in 7 Figure 2,22: The direct AND gate (2 inputs) Se << KS 3 inputea high yhe pute high trajectory with 2 inputs high 1 input high No input high SSA Voltage (mV) Figure 2. 23:6 the direct AND gate (3 inpute) E(mV) ° Voltage Volta ee. Page 56 Input Zs Output (Que) Negatively overbiased circuit Time (b) V Time y <n —_ — — --- Output (A) Input - output wavefarme Figure 2.24;- Signal modification prior to input to modified AND gate Page 57 a, Input —> —| RI —> Output ) i. overbiased Figure 2,25: COMPLEMENT circuit Non ground plane Y G~N SSssS . S| a tle Figure 2,26: The inverting transformer Zo ; 5 Zo Cc Figure 2.27: Approximate equivalent circuit of the inverting transformer Page 58 120 na coaxial 15 ns coaxial Pulse source > delay line >—| delay line (50 ohm) | (50 ohm) To scope To scope sync channel A Coaxial to microstrip connector To scope channel B ¥ 50 ohm ( Microstrip to ing: coaxial < INVERTER Termination connector Figure 2.28; Test circuit to measure the reaponse of the inverting transformer. Page 59 babs ee ee Input ho < Output Figure 2.29a:- Direct Microstrip Line Scale:- Hor. 5ns/cm. } < Input — i Se Output | | Figure 2.29b:- Inverted Microstrip Line Ty) = Fo = 1 inch. Scale:- Hor. 5ns/cm. Page 60 < Input | <— Output Figure 2.29c:- Inverted Microstrip Line Pr, == 1. 8 inches. Scale:- Hor. 5ns/cm. . Figure 2.29d:- Inverted Microstrip Line r,=T5= 2.3 inches. Scale:- Hor. 5ns/cm. Page 61 1 = 1, <— Input ee | P| -- } Figure 2.29e:- Inverted Microstrip Line r= 2.3 inches Fo wo Scale:- Hor. 5ns/cm. Page 62 PART 3 THE CONNECTION OF LOGICAL ELEMENTS In OR, AND and COMPLEMENT circuits the logically correct output depends only on the state of the inputs and accord- ingly these circuits must not respond to the pulses which return along their output lines. Since the tunnel diode is a two terminal device these return pulses must be attenuated, suppressed or cancelled. In this part some possible methods of connection of the logic elements of the previous part will be investigated the primary object being to make the diodes insensitive to pulses returning along the output lines but at the same time responsive to the pulses coming from the input lines. 1) Passive Network Coupling. Consider the two diodes A and B connected by a transmission line of characteristic impedance Zo in series with a linear passive bilateral network (N) as shown in figure 3.1, The Reciprocity Theorem (3) can be employed with the result that if the output of A can trigger B then the output of B can trigger A and vice versa if the diodes are identical and have the same load line and % bias. Hence, if the coupling is to connect the output of A to the input of B it is immediately seen that the necessary property of insulating A from the output pulse at B is not obtained. 2) Directional Coupling Using Blocking Diodes. When the network (N) of figure 3.1 is linear by the reciprocity theorem the current pulse I, produced at diode B when A switches is equal to the current pulse 1, produced at diode A when B switches. If N is a directional network the amplitude of these current pulses will be no longer equal. Defining the directionality D by the equation Ip max tamax D= Page 63 we see that the type of directional coupling needed is that which gives a high value to D since this effectively insulates A from the output of B. Suppose the network N at the input to B consists of a blocking diode in series with a transmission line whose characteristic impedance is real and equal to Zo as shown in figure 3.2. Neglecting the forward impedance of the diode the directionality factor D will simply be max D= 2max where Vin x and Vomax are the maximum values of Vi and v5 when a the diode switches from the low to the high state. An inspection of figure 2.8 shows that a good approximation to Vi when the D, C. bias value is removed is Vmax wt fl - Cos {( vt) \ 2t Vmax t > 2t )] O<t < 2t 1 as illustrated in figure 3. 3a. For low values of inductance and a tunnel diode of capacity C and peak current I, Zt, = 7 my secs, I p Since "return to zero'! A, C, bias circuits are of primary interest it will be further assumed that vy returns to zero giving mirror symmetry about 2t, (see figure 3. 3b) so that 1 Vmax 11 - Cos mt/(2t,)] O< t< 4t 2 Vit) = tt) 0 t > 4t, Neglecting A, C, bias noise and assuming the blocking diode has the equivalent circuit of figure 3.4 where ris zero if the diode is forward biased and infinite when reversed biased V, is simply as illustrated Page 64 in figure 3.5 where I and the initial voltage across Ca are zero at t=. The solution is -t/(C.,Z , V5 (t) _ e Cp 0) _ Sin {rt /(2t,) - e\ 2 2" Vmax 2 | 1+ 2t/(mCZ))@ afl + 2t,/(nC 25) for OSt< 4t _ ~1 where @ = tan [roy % 9/2) | The plot of Vo (t/t) )/V ax for various values of t/(CQZ,) is shown on figure 3, 6 and the directignality D = V is plotted /V max 2max against t}/CpZ, on figure 3. 7. EXPERIMENT:- The circuit schematically shown on figure 3, 8a was set up with co-axial circuitory,A 20 ma germanium strip line tunnel diode (R. C, A. IN3129) and an axial packaged germanium back diode (G. E. BD-3) were mounted in a modified BNC connector, The voltages vy and Vo were measured across 50 ohm scope terminations, The bias had the shape shown in figure 3. 8b and was fed through a 50 ohm transmission line the positive step being supplied with a repition rate of about 100/sec. The amplitude of this positive step was set to give marginal triggering of the diode. The oscillographs of the voltages vy and V5 are shown on figure 3.9. Clearly the experimental value of D = 3.5 and t= 0.6 mysecs. The value of the blocking diode capacity was 4pF thus making t,(CpZ5) = 3, From figure 3.7 the theoretical value of Dis 4.1. Hence, the experimental value is slightly lower than the theoretical and this discrepancy is mainly due to reverse conduction in the blocking diode and inductance in series with the blocking diode. A careful examination of Vo on figure 3.9 showe a elightly negative value of the voltage V; after the diode had switched and this negative overshoot is characteristic of series inductance, Page 65 Turning now to figure 3.10 which will be considered as an OR gate with two inputs and two outputs clearly the return pulse along the input line will depend on whether or not an input pulse appeared on that line. If an input pulse occurs only on line A then the input - output pulses will be as shown on figure 3.11 where the input pulse on line A is assumed to be some fraction of the output on line C or D, Initially the input pulse on line A is negatively reflected but is later positively reflected when the diode switches with the result that V x will be slightly greater than V Ama Bmax’ Because of this and the effects of the non infinite reverse resistance and the series inductance of the blocking diode the directionality as shown in figure 3.7 is slightly on the optimistic side. Consider a logical circuit with n inputs and n outputs, The return pulses along the n output lines must be equivalent to less than one input, To obtain a rough approximation to the blocking diode requirements assume that these return pulses should be at most equivalent to half an input. Psa. n- The third column of Table 3.1 can be then be constructed using figure 3.7, Ifa 20 mA tunnel diode and a 25 ohm load line are used and the output impedance of an input line is assumed equal to D Zo then Dz. /n _ Oo - 25 1+ D or Zo = 25n(1 + 1/D) Assuming the minimum values of D the values of Ze corresponding to the given values of n are then obtained. An inspection of figure 2.14 reveals that a value of 7 < 1.5 is reasonable and if the capac- ity of the 20mA tunnel diode is less than 1) pF (e.g. R.C.A. type Page 66 TD182) then from equation 2.9 t, < 15 10/20 < 0.375 mp secs Z TABLE 3.1 n D t)/CpZo Zo Maximum blocking (20mA tunnel diode) iode capacity ( B) t,= 0.375 mu secs. 2 >4 > 2.8 62.5 2,14 pF 3 1>6 | >4.5 87.5 0.95 pF 4 >8 >6 . 112.5 0. 56pF The maximum permissible values of the blocking diode capacity (column 5 of Table 3.1) are now easily determined since Z9 and the upper bound of t,/CyZo are known for the given values of n. These maximum values are extremely low especially for n>2. Even with n = 2(i.e. two inputs and two outputs) a blocking diode whose capacity must be about2pFthrough which a 29 mA tunnel diode can be triggered from the output of a similar stage must be found. It should be remembered that Zo is inversely proportional to the peak current (I) and the maximum permissible blocking diode capacities are accordingly proportional to T. Hence, by using a 109 mA tunnel diode with an T/C ratio of 2 mA/pF and blocking diodes of 4pF it is possible to achieve the necessary directionality for an OR gate with n= 3 (three inputs and three outputs), Some improve- (4) ment can also be obtained using multistage current amplification. * Examples of 4pF blocking diodes are: - 1) R.C,. A. type nos, TD-151 and TD~152 2) G.E. type no, 4JF2-BD3 3) Page 67 Apart from the high power requirements this approach has two major disadvantages. | 1) The non linearity of the blocking diodes gives severe harmonic distortion of a sinusoidal clock. 2) In the case of an OR gate driving a modified AND gate or a COMPLEMENT gate the blocking diodes will allow the negative return pulses to pass thus destroying the logic of the OR gate. While the first of the above two objections could be overcome by using a suitably phased ''spike" clock or a synchronous d.c. biased monostable circuitry (presumably using inductive switching) the second is a far more serious problem. In the following sections of this part an alternative coupling method permitting direct connection of the simple logic elements of Part 2 will be studied. Syuchronized Coupling Techniques In the previous section no effort was made to utilize the clock phase as a possible method of suppression of the reflected pulses (i.e. these pulses that are incident on the output terminal of a diode). Suppose in figure 3.12 the A.C. phases of diodes A and B can be arranged so that when A switches its output pulse reaches B when ER is a maximum but when B switches it output reaches A when EA is aminimum. Then, except for the effects of multiple reflections, the necessary directionality is obtained and logical information will propagate from A to B as indicated by the arrow on figure 3.12, Due to the fact that the output of A (if high) will lag the clock by about 1/4 of the clock period (figure 3.13) it is impossible to obtain the correct phase at B without a loss in the transmission line. Suppose in figure 3.12 that the delay time of the line is TH vy (3.1) vet 2 Page 68 where T is the clock period, j is an integer > 0 and O< Vy < T/2. Then for optimum suppression the pulse arriving at A from B should have its maximum when the clock at A is at its lowest point. Accordingly if the switching delay is vo as illustrated in figure 3,13 then ZV, + 2v, = 6T + T/2 (3.2) where § - 0 or land the clock at B must lag that at A by the time interval At= ¥, + ¥ (3. 3) Since the maximum operating frequency will roughly correspond to a value of v 2 = T/4 this value of Vo will be assumed. 1) j odd If n is odd equations 3.1, 3.2 and 3, 3 become v, = 0 (3, la) y ze T | (3. 2a) 2 At = 3T/4 (3, 3a) Essentially then the logical elements must be connected by delay lines whose lengths are odd multiples of the half wave length (at the clock frequency) and in the direction of propagation the phases of the A, C, voltage across successive diodes must lay by an angle of 3r/2, The problem now is to design a system with these two properties, Consider an infinite chain of identical diodes in the low voltage state with each one connected to its nearest neighbour by 1/2 wave length lines all of the same characteristic impedance Zo and fed through a bias resister Ro with A, C. superimposed on D, C, and the applied A.C. phase at each station lagging the one on its left by 31/2 as illustrated in figure 3.14. From symmetry the combined effects Page 69 of the clocks applied at stations B and D will produce a standing wave of zero amplitude across the diode at station C, Thus the voltage across the diode at station C will not be altered by the presence of stations B and D and the traveling waves originating at B and D will not be attenuated at C and similary those originating from E and A will not be attenuated at D and B respectively. It will be now assumed that the impedance of a diode in the low state is constant, This is equivalent to saying its series inductance, capacity and the slope of its V-I curve are ail constant in the range of the A.C. oscillation (see figure 3.15). Then the voltage across each diode will be sinusoidal and of equal magnitude and if the phase across the diode at Cis /a then from symmetry that across B and Dwill be /1/2+q@_ and /-7/2+a@_ respectively and soon, Hence, if V is not equal to zero the primary requirement for directionality is achieved. The magnitudes of V and a can be calculated in the following way. In figure 3.14 there is between station C and E a line of unit wavelength with opposite voltages at its ends. The transmission line equation then is Vio = Via + CoshfL - 1,Z,Sinh[L (3, 4) where I. is the current supplied to the line at C and fL= al + jBL (3,5) BL= 2r (3. 6) e** = line attenuation (X) (3. 7) From equation 3.4 Vie Sinh TL I,Zo 1 + Cosh [PL and using equations 3,5, 3.6 and 3,7 Page 70 Via X-1 IZ OxH Ss (3. 8) Hence, the A. C, bias voltage Vila at station C is unchanged when the circuitry to the right and left of C is replaced by an infinite - ly long linc of characteristic impedance “z 1 0 xX -1 (3.9) 2 a +1 The equivalent A, C, bias circuit is theu that of figure 3,16 where the A, C. bias (E/0 ) is equal to ESinwt. Clearly V = 0 for lossless lines (X - 1). It is of course possible to increase the length of the coupling lines by any multiple of the wavelength (at the clock frequency) and the attenuation X will be that along a length of line equal to twice the coupling length. 2) Finite chain of diodes (j odd). Suppose that there are no diodes to the right of B in figure 3.14. It is possible to simulate the effects of the missing diodes by a stub transmission line suitably terminated. The infinite chain of figure 3.14 consists of two independent infinite chains as shown in figure 3.17 since the diodes of one chain are at the points of zero standing wave amplitude of the other chain. The voltage on the line between stations B and C is then the superposition of the voltages due to the two independent chains. Using the notation of figure 3.17 xX +i 1 Vila [ cosh py - x Fi i Sinh [7 y | “9 x - 1 x - i wy Wa Page 71] and a x BE, = jV/a | ._£ + jV/a a “4 L x - 1 ~— X.~ J W Wy where 1 . P= a@ + iB . BL= 2m and 1 ab= X e Clearly there are four traveling waves (wo), Wo, Wa, and w4) betwreen stations Band C., The twro waves e2 and wo are moving from C to B and O} and Wy are moving from Bto C, also, Wy and W3 have the same phase at BZ = 1/4 (i.e. By = 30/4) and the ratio of their amplitudes is fo,/ log! | BZ = 1/4 1 2 L/4 = x 1/4 at the same point Wo and Wy have the same phase (opposite to that of wy and W3) and the ratio of their amplitudes is log! _ a hl4 1/4 = = xX Joon! | BZ = 0/4 Accordingly the effects of the diodes to the right of B can be simulated by a 1/8 wavelength line identical to the coupling lines and 1/4 terminated to give a positive reflection coefficient of 1/X Since x \/4 is the two way attenuation factor of the 1/8 wavelength stub line a positive reflection coefficient of unity could also be employed if the attenuation factor of the line were squared. A short circuited 3/8 wavelength stub could also be used. Hence, with coupling lines that are odd multiples of the half wavelength a 1/8 wavelength open circuit Page 72 or a 3/8 wavelength short circuit stub line can be used to terminate at the receiving end * of an infinite chain of diodes. A similar analysis for the sending end * results in a 3/8 wavelength open circuit line or a 1/8 wavelength short circuit line. The two way loss in the shorted or open circuited stub must be always equal to the one way loss in the coupling lines. 3) j even (wavelength coupling lines), If the length of the coupling lines is some integral multiple of the wavelength then the direction of propagation will be the reverse of that for j even, The infinite chain can also be terminated and the correct termination at the sending end is the same as that at the receiving end with j odd and vice versa. Again the two way attenua- tion in the stubs has to be equal to the one way loss in the coupling lines. 4) Multiple Reflections. Multiple reflections between diodes cau be divided into Lwo classes namely those due to negative reflections of trigger pulses (class a reflections) and those duc to negative reflections of suppress-~ ed pulses (class b reflections). Class a reflections The output pulse from a diode (A) impinging on the next diode in the direction of propagation (diode B) will be initially negatively reflected at B and returning to A will be again negatively reflected so that it will reappear at the input to B an integral number of bit times later and may now lead to false triggering of B unless it has been sufficiently attenuated by the coupling line. Clearly class a multiple reflections have the worst possible effect when the line is distortionless and the reflection * i.e, the end towards which the logical information flows. tek i.e. the end from which the logical information flows. Page 73 coefficients are -l. The effect is then equivalent toa directionality factor X where X is the two way attenua- tion of the coupling lines. In multiple input-output circuits class a reflections limit the fan in and if this is equal to n and these reflections can at most be equivalent to some fration @ of an input then n=<axX It should be noted that termination of the lines at the input or output will overcome this effect but a loss in gain will result. Class b reflections In figure 3.14 the pulses originating from C will be suppressed at B with a negative reflection coefficient close to unity. Returning to C these will be again negatively reflected so that they return to B with the same polarity and are again suppressed. If these pulses are attenuated without distortion (Heaviside line) the effect can be tolerated but in practice the attenuation will be low at D. C. and increase with frequency. Accordingly the pulses will spread and cause significant shifts in the D.C. bias except in the simple case of a closed chain of OR gates. In this latter case the D.C, shifts introduced at a diode by the diodes at both sides of it will have opposite sign. In _all other cases it is necessary to terminate at input(s) or output(s) of each gate. 5) Except for the closed chain of OR gates which will be later considered as a register or memory device from multiple reflection considerations it is necessary to terminate the transmission lines connecting the logical elements at least at one end. Termination at both ends will further reduce retlections and the current which must be suppressed by the clock thus enabling the circuits to operate with Page 74 With terminations at one or both ends the Table 3.2 shows the dependance of the required gain (the G parameter of lower A, C, bias, correct phasing can be obtained with lossless lines, figures 2,14) on the terminations when the attenuation factor of the coupling lines (all having the same characteristic impedance Zo) is equal to VX", the fan in and fan out ratios are nandm respec- tively and the load line is invariant with respect to the termination or the fan in and fan out ratios. In the non terminated case it has been shown from A.C. bias consideration that the TABLE 3,2 Termination Type G/Af x Comments Not terminated — + Multiple reflection 2 2 problems Terminated at input +m Class a reflection 2 eliminated. One class b reflection Terminated at output n +m One class a and one va class b reflection Terminated at both a loom Class a reflections ends eliminated. No class b reflections characteristic impedance of the connecting lines was reduced by the factor so that only in cases where X must be high such as in x +1 a dynamic register or memory device where a large number of bits are stored in a delay line can the non terminated case be justified. In the logic matrix where the connecting lines will be no longer than a few wavelengths then X will be virtually equal to unity and since Page 75 it will be later seen that the gain demands are easily met termination at both ends is optimum in these cases for the following reasons:~ a) Reflections are kept to a minimum as are the currents which must be suppressed by the clock b) The circuits are symmetrical, the circulating currents in mixed bias circuits are reduced and the D.C. short of the necessary transformer in the complement circuit is removed, 6) Fan in and fan out With a fan in of n and a fan out of m and termination at both ends the value of the gain (G) must he G= mtn (3.13) If a value of r is selected then figures 2.14 give the maximum value of m + nasa function of the percentage bias, For example a 7 of 1.5 my secs/pF/mA leads to the following values of m + n for different % bias levels:- % Bias Maximum value of m +n for 7 = 1.5 97,5 8 95 . 6 92.5 4 If a lower value of + had been selected the maximum permissable values of the sum of the fan in and fan out integers would be also lower. This implies a compromise between maximum operating frequency and fan in fan out. Since all the coupling lines should preferably have the same characteristic impedance the peak Page 76 current of the tunnel diode must be proportional to m + n and the % bias must increase with m +n. 7) The A. C. Bias Amplitude The A, C, bias amplitude must be large enough tu puarantlee reset. However, if its amplitude is extremely high the load line will drop below the diode characteristic before the diode can switch. Hence, the optimum A.C, bias is the minimum value which guarantees reset, Here the suppressed currents must be taken into consideration since in the connection of like biased circuits the action of the suppressed cur- rents will be to increase the diode current thus tending ta impede reset or cause switching during the negative part of the clock cycle, Suppose the diode in figure 3.18 has a fan out of m, The maximum suppressed current (I) will occur when the diode is low and return pulses occur on all the output lines and at a time when the A.C, bias is low. Hence, the peak to peak A.C, current (In c. p> p) must be greater than I max and so TA Cpr>p>m /Nout/ 2Zy and in dimensionless form Tac, p>p , m/Vout/ 1 I 2 IZ p p 0 In the above I, and (Vout) are respectively the peak current of the tunnel diode and the output amplitude when the diode switches, Since 2Z4 ; Ey mtn I p the above equation becomes : it . m/Vout/ AZ A.C. p > pi*P 2z (m + n)E 0 0 1 {Vout / > (l+n/m) Ey Page 77 Also, from figures 2,14 E) should be about 500 mv and / Vout / would then be about 359 mv. The above inequality then becomes TALC. po>P yx 0,7 I 1+n/m p Accordingly if the peak to peak A.C, current is 70% of 1 the diode when low will not be switched by the suppressed currents. More generally the ratio of the A. C. peak to peak current to the diode peak current must satisfy the inequality /Vout/ wm I A.C. p >P ys Eo I Pp metiea=n where Mey is the net number of return pulses with the same polarity as the D,C. bias. Return pulses of opposite polarity count as a minus one in myy. The maximum value of My is accordingly m, The above inequalities are applicable only when the diode is in the low state. If the diode had been high the return pulses will tend to inhibit resetting and this will invariably be a more stringent restriction. Using the circuit analyser a dynamic analysis was performed to study the effects the suppressed currents, the operating frequency and the % A.C. bias have on the performance of an OR gate when the combined uumber of inputs and outputs is 8. The tunnel diode circuit is shown on figure 3.18 and the Thevenin equivalent is shown on figure 3,19, Since a gain of 8 [equation 3. 13] is required 97. 5% bias was selected. Essentially there are four variables: - a) My which is the net number of return pulses (return pulses of opposite polarity to the D.C. bias count as minus 1). b) The % A.C. bias (i.e. (I, Cp p/ 1p) Page 78 c) The per unit operating frequency f=fC/l =“ C/L P au " PB d) The load line which determines the magnitudes of the A.C, and D.C, bias. The above factors (a), (b), and (c) have at most a second order effect on the optimum value of the load line. Accordingly the bias was selected from figure 2.14C and is about 500 mv. The A.C. and D.C. bias then make E(t) = A +B Sint where A + B= 500 and the ratio B/A determines the% A.C. bias. Next an approximate form was selected for the input and return pulses, The form selected for input was 0 t <0 et) =4229 [ 1 - Cos 2ut | O0<t< tf 2 0 t > w/w and the return pulses were assumed equal to f(t-7rAw. Hence, E, = A + BSinot + Kitt) my, E(t - whe) where k is the number of high inputs [ k was always taken equal to unity since this is the worst case |. Computed dynamic trajectories are shown on figures 3, 29, 3,21, 3.22 and 3,23. Figure 3.20 illustrates the effect of the % A.C, bias. The amplitude of the ouput signal decreases as the % A.C. bias increases but the rise time is not seriously affected. On figure 3,21 the %A.C, bias is held constant at 80% and the frequency is varied. Figures 3.22 and 3, 23 show the effect of my; on the reset and with 60% A. C, bias the maximum permissible value of m,; is Page 79 3 but with 80% A.C. bias m,, can be as high as 6 (m,,= 7 also O.K, in this case but marginal). Clearly there is a compromise between the value of May and the operating frequency. As m,, increases the % A, C, bias must increase to guarantee reset and to maintain the same output amplitude the frequency must decrease as the %A.C, bias increases. In the cases examined (m +n = 8) 80% A.C. ‘bias gave the necessary output amplitude to give a gain of 8 at values of f up to 0.15 (Kilomegacycles /pF/mA) and the suppressed currents did not cause false switching for values of m,, < 6. Hence, the maximum operating frequency in this case is about fmax = 0,15 1,/C Kilomegacycles If the number of inputs and outputs is less than 8 the reset problem will not be as serious. Accordingly with diodes whose rfc ratio is 2 mA/pF it is possible to operate at frequencies up to 300 megacycles with m+n < 8 and my, < 6. On the other hand figure 2,i4c predicts a value of 7 of about 1.45 my secs/mA/pF at a gain of 8 and 97.5% bias and when this value is inserted in equation 2, 20 the value of fmax obtained is 0.175 1_./C. Hence, a slight discrepancy is evident and the value of 7 in figuresil4 when inserted in equation 2.20 gives a slightly optimistic value of fmax. Other cases examined gave somewhat similar discrepencies and a more conservative and accurate approximation to fmaxis fmax = —i (3. 13a) 57¢ C/I 7 C/T, where, as before, 7 is givenin figures 2.14, 8) Phase Identification and the Connection Rules. The four phases are numberedl, 2, 3, and 4 and their schematic vectorial and voltage time relations are shown on figure 3,24. The phase numbers are mod, 4i.e. phase 5 and phase lare the same etc. a) Directional coupling. The gate driven by phase i can be connected to Page 80 that driven by phase i+ 1 or i ~ 1 and the direction of propagation will be from itoitiori-las indicated in Table 3.3 where n = 0, 1, 2, the total delay is the time interval (in bit times) and between the arrival of the input to one gate and the occurance of the output at the second gate. minimum delay per stage of 1/4 of the bit time is due to the clock phases rather than the rise time of the diodes. It should be noted that phase i cannot be connected to itself or phase i+ 2 if directionality is required. TABLE 3,3 D.C. Bias Direction of Length of connecting Total Propagation transmission line Delay in in wavelengths bit times Phase i and itoit+l n n+1/2 i + 1 both itltoi n+1/2 nt positive or both negative Phase i itoit¢l n+1/2 n+l positive and | i 41 toi n n+1/2 i+ 1 negative Phase i itoitl n n+1/2 negative and | i 41 toi n+1/2 n+ 1 i+ 1 positive Page 81 b) Bi - directional Coupling. If two diodes A and B are connected so that A can drive or inhibit (or contributed towards driving or inhibiting) B and vice versa then the coupling will be termed bidirectional. With the four phase clock the only bidirectional couplings are where a diode whose A.C. phase is i is connected to another where A. C. phase isiorit 2. Bidirectional coupling can sometimes be employed to reduce the number of gates and delay time of a logical network. An example of this type of coup- ling will occur in the addercircuit [figure 3, 29. 9) Diode Bias and Power Requirements, Here it is assumed that the diodes are interconnected by terminated lossless delay lines of characteristic impedance Z,,. When the diodes are interconnected the A. C, voltage across each one must be one of four phases in quadrature. Assuming this is so the A.C. power required by each and the relative phase of its driving voltage will now be determined, The A.C, current T, through any diode A whose A. C. driving voltage is Eis given by the equation ~ Ey ~ v, > VLA, - Vv, I = + (3.14) a Rg. x 2Zq where Vv, is the voltage across the diode A, Ro is its bias resistor, wv is the voltage across the diode X to which A is connected and K. is a rotational vector depending on the length of the interconnecting line. If = VE. = 0 then the neighboring diodes have no effect on the bias of diode A and for simplicity we will say that diode Ais A,C. balanced. In this case equation 3.14 becomes B -F. v TseeSe 4 -(m +n) — (3.15) Ry 2Zg Page 82 where m and n are the fan out and fan in integers respectively, The power Pp which is supplied is then given by the equation g ¥ q “<> When ES is eliminated by means of equation 3.15 (m +'n)R Pony eys [is 0 |(mtn) 52 a 225 ZZy ALN (m + n) Ro + vo i+ ——_— Za and if Ry = 27. ,/K | (3.17) then 2 B.—ee + fie Bee manly,’ K K 22.5 a “™ Vt & | (3. 18) aa K Remembering that the gain equation 3.13 is valid only when Rg >> aZo the bias resistor is equivalent to K outputs and equation 3.13 now becomes G= mintkK (3.19) Hence, a further compromise exists between the A, C. power, gain and fan in fan out integers, Example: - Suppose a value of 7 of 1.8 is selected, Then from figure 2,14c the maximum value of Gis 9, Assuming E, = 500 mV anda 20 mA tunnel diode is used then the A. C, power dissipation is that shown on Table 3,4 for varying K on the assumption that m + n+K = 9, Page 83 Ve and I are in phase and 80% A.C, bias is employed. Clearly fro:m Table 3.4 the A.C, power is almost directly proportional to Ro which is reasonable since the diode is a low impedance device. Also the power even for K = 1 is not excessive. TABLE 3.4 K mtn Ro P (milli-watts) 1 8 225 9,0 2 7 112.5 4,5 3 6 75 2.9 While the results in Table 3.1 were computed for A.C. balanced diodes when a diode is not balanced the A.C, power dissipa- tion will not change to any great extent. Ro could consist of a physical resistor Ry" connected to a low impedance (Z) power supply line where ste and in this way a number of diodes could be fed from one power line. | The coupling through the power line between any two diodes will be suppressed by the A. C. phase but neglecting this it is at most equivalent to gain G. where G. = m+n tk ZylZ (3. 20) -K Hence, in the previous example if ZZ =10 (i.e. Z = il. 25 ohms) then G. is equal to 90, 40, 30 for values of K=1, 2, 3 respectively. *A delay line of characteristic impedance R, matched at the power end to a low impedance (Z)} power line is also feasible. Page 84 Since the lower of these values is considerably greater than Gmax at 97.5% bias and there will also be extensive suppression of the coupling due to the phasing the coupling through the power lines will not be severe. In a tunnel diode which is not A. C. balanced the only serious consequence will be a phase shift in its anode voltage. This can be corrected by a slight phase shift of its driving voltage computed by means of equation 3. 14. 10) The Generation of Boolean Functions. The logic elements of Part 2 consist of diode circuits which are positively or negatively biased. The diodes can also be under or over biased. The input-output signals are positive (weight +l), negative (weight -1) or virtually at ground potential (weight 0). The output of a positively (negatively) biased circuit then has weight +1 (-1) or 0 aud is a function of the algebraic sum § of the inputs** There are four classes of diode circuits and these are shown on figure 3. 25. On this figure the cquations giving the output weights for cach clase are also shown together with the representation of the inverting transformer which essentially changes the sign of a signal weight. The inputs and outputs can be indicated by arrows on the connecting transmission lines but for directional coupling the connection rules of Table 3.3 must be satisfied. In cases of bi- directional coupling arrows will be shown pointing in both directions on the transmission line. Figures 3,26 and 3.27 schematically illustrate the generation of a minterm and a maxterm respectively and a full serial adder is * i.e. weight +I (-I) is associated with the output pulse of a posi- tively (negatively) biased tunnel diode when this diode switches into the high voltage state. The weight 0 is associated with the output voltage of a tunnel diode in the low state. *~ More correctly S is the algebraic sum of the input weights (e.g. if there are four input lines and the input pulses on these lines have weights +1, -1, +l and 0 thesS = +1). This algebraic sum if the gov- erning parameter because current summation occurs at the input. Page 85 shown on figure 3.28. While some minterms and maxterms can be generated in less than 1 bit time if one hit time is allowed the max- imum number of terms possible in a maxterm is i (2n for a minterm) where nis the fanin ratio, The adder has a two bit time delay. Clearly if the outputs are functions of the inputs only any Boolean expression can be generated and the delay in bit times will depend on the complexity of the outputs, In this case information can be supplied to the inputs at the clock frequency. However, where the outputs or internal states have to be fed back as inputs then it may be necessary to introduce certain dead periods and information must then be supplied to the inputs at a sub multiple of the clock frequency. Redundant elements can be employed to reduce or eliminate the number of dead periods and bi-directional coupling and internal feed back loops can also be employed to this end. In the adder circuit the dead period was eliminated by these latter methods. No general method of evaluation of the extent to which dead periods must be introduced could be found and no existing theory seemed applicable. * On the other hand, a brief investigation into the logic equations of the LGP 30 computer indicates that inputs could only be supplied on every 5th cycle because of feed back restrictions. This, however, cannot be considered as a truly indicative result since the logic equations of the LGP 30 were minimized to suit the circui- tory. The great advantages of simplicity of the basic logic circuits coupled with their high operating frequency and the simplicity of the connection rules are of sufficient merit to stimulate further investigation on the part of logic designers at least for some special purpose applications. In Part 4 a possible application to high speed memory devices is outlined. «The possible application of Markov processes was suggested. Page 86 Summary:- Passive network coupling or directional coupling using blocking diodes cannot be employed to couple the logic elements of Part 2. Apart from the low capacity restrictions on the blocking diodes they are completely ineffective when directionality is required between positive and negative biased circuits. On the other hand, phase techniques incorporating clock. suppression of extraneous pulses proved to be a feasible method of connection of the logic elements and multiple reflection are eliminated by termination of the delay lines. The use of a bias voltage consisting of A.C. superimposed on D.C, where the A. C. amplitude was sufficient to guarantee reset did not seriously alter the value of the available gain and the zero to 90% rise time was in good agreement with the value deducible from parameter 7 of Part 2, The power requirements are low and cross coupling through the power lines will be partially suppressed by the clock phase. The connection rules are reasonably flexible and more than one configuration is possible for the generation of most Boolean functions, The only essential limitation is that the connection rules remove complete generality as to the types of Boolean functions that can be generated ina bit time. This restriction can always be removed by introducing p dead periods after each live period, In most cases p can be reduced or eliminated by redundant circuitry and bidirectional coupling and will rarely be greater than 2 or 3, Page 87 RANI, Zo “IN. fawa A. 5B Figure 3.1:- Passive network coupling. Zo Vit a AN, Zo Figure 3,2:- Directional coupling using blocking diodes. Vv v ~ Voltage Voltage ry 5 @ wa 2t 4_ 7 PEO {a} (b) Figure 3,3:- Output voltage waveforms. Page 88 Figure 3,4:- Equivalent circuit of the blocking diode. Figure 3.5 ‘asuodsoa oporp Burmoots -19°¢E Sanst se OZ E54 = BAIN. UO SONTeA S°0 xeu 2 ALVA Directionality IS4 10 4 On Jase Page 90 2 q } 8 10 ty/ Cy Zo Figure 3.%:- Directionality vs. t)/C,4 Page 91 E 50 Es Trigger point o >I Oo o ° Time (a) (b) Figure 3.8 | Tne <9 Scales:- Hor. “Oo dnelan We Ver. son om. Figure 3.9:- Response of the test circuit of Figure 3. 8. Page 92 input Output (Line A) (Line ©) Tmput - Output (Line 8) (Line D) Figure 3.10:- input-output configuration _- Sutput (Lines © and Dj - kz _.»~ Input (Line A) a © _- Output (Line A) 8 a “ rea va > f | _.- Output (Line 5) a A \/ Va — Figure 3.1h:- Input-output waveforms of the circuit of figure 3.10 when an input pulse occurs only on line A. Page 93 Ep Es —_—__> an Ze nwa A B Voltage Time o Figure 3.12;- Directionality by phase techniques Voltage Time Figure 3.13:- Delay time of a tunnel diode circuit Page 94 APTRUOTISIIp IOJ squautaatmnber os ey “pT '€ oan3r gy nding IN ci al 2 & Vv (ez ‘ TH (ez < % ) WN ( °Z c %) AS) Coz! Ty) WI woryesedoad jo uwo19911q Current A.C, Current Range Page 95 A.C. Voltage Range > Voltage Figure 3.15 Elo ? 8 N t U fe Figure 3.16 The equivalent steady state A. C. load of figure 3.14 Ls Py les < L Fs penn Ne v4 M B D 9 Lt Lo [or < L >| < L_——»> 3<—— KZ Et na na A om e Figure 3.17 n input lines each of charac. teristic imped- ance 4 ° m output lines each of characteristic impedance Ze Figure 3.18:- Terminated input-output lines Ett wal Figure 3.19:- The Thevenin equivalent of figure 3.18 Page 98 (Aur) o8e3z10 4 00F 002 oot Azoyoofery stureudp ayy uo seiq °9 “Wu ayy Jo JOFFE OUT, -ig7‘¢ ean3i sz SUIT} JURISMIOD - WOOT OR ~~ %09 ~ A ysiyq gndut | d vu/ad/s,O°N ST O/T ST'O ri on- Lag SIQEIICA SBI “QO °Y% - B= Ur T/T Azoyafery stureusp ayy jo souepusdep Aduenbary ayy, -i17°¢ sant Page 99 {AtL) a8eqod one 002 t * U ro d q T/I yu/agd/s,O ‘WS I/O} = se9aaro uo sonter ysty yndut { on= Ay %Og = SBIC “DWH g = U4 Page 100 SEIQ °D ‘W%09 32 Fou uo Azozafeay atureudp 9yj Jo souepusdap ayy, -‘¢7z°¢ canst az {Aua) e8eqJo, 00% 00€ 00z 00T 0 + + Tr t Hg HG * d + uSty yndut 1 it yu/ad/s,o-Wwes O/dt st-o =] atqerae,a Fux @ = ws 4+, set “DO “WV %09 ' Page 101 SeIq "OD "yw%0g 12 ur uo ATO}DalVIZ DIWeUAP By Jo satiepuadap az, (Aur) e8eij0 A 00F 00 00z ogt -i¢7°€ ornsrs7 + 4 7 ys1y yndut | d vu gTd/S,O°Wst O/ IGt’o =F aTqeuie, Foy € = Utu SeId ‘O°vV H08 Page 102 Voltage A i 2 3 Yo t z >! > Time Ve 2 Le Figure 3.24:+ Phase identification NN : Class 1 phase i Positively underbiased circuit 5 iol {* , SB) i Output weight = 0,8 <) — a“ Class 2 phase i Positively overbiased circuit ; . +1 , 3 20 1 Output weight = do ,$ <0 Class 3 phase i 2 KN Negatively underbiased circuit i Output weight = {| Ss! o ,S yt Class 4 phase i Negatively overbiased circuit Output weight = {! » S £0 0 », S?O0 inverting transformer Figure 3.25:- Schematic representation of the basic logic elements and of the inverting transformer Page 103 I D/n (41) AtB+Cad Vv Figure 3.26;+ Generation of the Maxterm A+B+C+D te Figure 3.27:- Generation of the Minterm ABCD Page 164 n n n-1 n° nel Figure 3,28:- The full adder circuit Page 105 PART 4 MINIATURE ELECTRICAL DELAY LINES In present day digital computers electrical delay lines are pre- dominantly employed as a connecting device between various elements and essentially no effort is made to make the delay time of these lines an important factor in controlling the logical operations of the com- puter, since to do so the lines would be extremely long and expensive. Tunnel diode circuits, on the other hand, have the single predominant advantage of extremely fast switching speeds, thus bringing the length of the delay lines well into the range of practical application. In Part 3 it was shown that a delay time was sometimes nec- essary in the device connecting the logic elements of Part 2. Apart from satisfying this necessity electrical transmission lines have the following advantages when used with tunnel diode circuitory:- (a) Delay lines and especially strip delay lines can be easily integrated into tunnel diode logic circuits. (b) They can be employed as dynamic storage elements” capable of holding a large number of bits. (c) Since a delay line can be looped to return to its starting point or near it or can connect distant points the individual tunnel diode circuits can be close together or far apart as is required by the particular application. (d) When logic elements are connected by electrical delay lines parasitic effects will be very low. (e) Since it is feasible to use delay lines of small cross sec- tional area (hence, the name ''miniature delay lines") there is a strong probability that extremely low volume circuitory will be obtained. * The word dynamic is employed here to indicate that the bits of information move in the storage element as distinct from core or drum storage where the bits remain in a fixed position. Page 106 Some miniature delay lines were constructed and tested. The configuration selected consisted of a centre strip copper conductor sandwiched between dilectric sheets with copper ground planes as shown in figure 4.1. This configuration was selected for the following reasons: - {a) Standard photo etching techniques were available to give the required centre conductor configuration. (b) It gave a solid construction and the ground planes would provide the necessary isolation. (c} Compactness could be readily achieved by stacking the layers one on top of another. In the experimental tests the response of the lines was meas- ured for an input pulse which, except for amplitude, would closely correspond to the output pulse of a tunnel diode when it switches ina return to zero system operating at about 400 megacycles. The attenuation of the pulse amplitude and the pulse spread were of pri- mary concern. Delay Line No. 1 Using the results of reference (5) this first line was designed to have a characteristic impedance of 50 ohms. This value was selected because the test equipment (oscilloscope, pulse generator, attenuators and connectors) was designed to operate with 50 ohm coaxial transmission lines. Since the velocity of propagation in the miniature delay line is inversely proportional to the square root of the relative permeability of the dilectric and a pulse has components of all frequencies an insulating material whose relative permeability is independent of frequency was required. In addition, the insulating material should also have a low loss tangent and so teflon” (relative permeability 2.1) was selected. The dimensions and spiral are shown on figures 4.2 and 4. 3 * Trade name for Polytetrafluoroethylene manufactured by DuPont. For details see Reference 6 . Page 107 For the photo etching process a ten fold magnified drawing of the spiral was made which was then photographed to give the correct negative size. Standard photo etching techniques were then employed. In this first delay line the inner end of the spiral was left open circuited and since the dimensions were small the outer end of the spiral and insulation thickness were expanded for connection to a 50 ohm coaxial line. The details are shown on Figs. 4.4 (a), (b), (c) and (d) and photographs of the constructed model are shown in Fig. 4.5. The test circuit and input-output pulses are shown in Fig. 4.6. A fourier analysis was performed to check the results against those predicted by the existing theory.) The comparison was made between the fourier transform of the output and its expected fourier transform. The results are shown on Fig. 4.7 and the agreement is good except in the D.C. region. The reason for the low frequency discrepancy is that the theoretical attenuation (A) in db/unit length is “a = Al Sec 4 27.3 Mie tanf& (4.1) where A depends on/k — Zo: tan$ is the loss tangent of the material and feMC and A are the frequency in kilogmegacycles and the free space wavelength respectively, implies zero loss at D.C. and so assumes zero D.C. resistance which is not so in this case. As might be anticipated, the discrepancy becomes pro- nounced when the skin depth is no longer small in comparison to t/2. An inspection of Figure 4.7 indicates that the error is appre- ciable for frequencies less than 100 megacycles at which frequency the skin depth is approximately equal to t/4 (i.e. 1/4 mill.). Since equal and opposite D. C. currents can be considered as flowing up and down the line which is terminated in its characteristic impedance the D.C. voltage drop = RI = RV/Z) where V = input D.C. voltage and R = D.C. resistance of the line (both ways). In this case R = 10 ohms and Z, = 50 ohms, giving a 20% drop at D. C. which agrees with the experimental value. Since pulse attenuation and spread are of primary concern, a Page 108 design criterion simpler than the fourier analysis approach was desired, Superposition is permissible and since the input pulses would approximately have the simple form ce) t< o . ] = Ss f(t) A Sin 2 w ft re) t <aF 1 where f is obtained from the idealized input shape the output ampli- tude can to a high degree of accuracy be obtained from the sinusoidal attenuation at the frequency f provided the pulse spread is not too great. This is illustrated diagrammatically in Fig. 4. 8. In the case of delay line No. 1 Fig. 4.6 shows that this method of prediction of the output amplitude could have been employed. For the dimensions of the delay line equation 4. 1 becomes a9 = 1.66 f + 132 (tan 6) f KMCG dh/meter KMC (4. Ic) From Fig. 4.6 f_KMC = 0.4 and so @= 1.05 db/meter. The length of the line was 2.88 meters (5.76 meters both ways) giving a theo- retical attenuation of 6 db or an attenuation factor of 2 which is in exact agreement with the experimental value (Fig. 4. 6). A discrepancy was detected in the delay time. The theo- retical value of 27.8 mp secs. was about 7% in excess of the measured value of 26 mp secs. This effect, which occurred in other delay lines, was due to the air gap betweenthe teflon sheets. The cross coupling between successive turns in the spiral produced no measurable effects so that the dimension a of Fig. 4.2 could apparently have been reduced. Delay Line No. 2 In Delay Line No. 2 the parameter a of Figure 4.2 was * This was computed on the assumption that the transmission velocity was equal to c/fk where c= velocity of light in vacuo and k is the relative permeability of the dielectric. Page 109 reduced to 50 mills thus giving greater length per unit area of trans- mission line. The spiralis shown in Fig. 4.9 and the construction, assembly and test circuit was identical to that for No. 1. Input-output pulses are shown on Fig. 4.10. The pulse spread is more significant than that for delay line No. l and the attenuation factor is about 3. The length of the spiral is 4.7 metres (9.4 metres both ways) so that the expected attenuation from eq. 4.lcis1.05x*x 9.4 = 10 db or 3.16. The attenuation obtained is slightly less than that theoretically expected and this discrepancy is clearly the result of overlap between pulses B and Cin Fig. 4.8. The expected delay was 45 my secs. and the experimental value was 42 mmsecs. again indicating an error of about 7% Delay Line No. 2a This is identical to No. 2 except that the three outside turns of No. 2are removed. It was first tested as in No. 2 and then immersed in oil” whose relative permeability was 2.2 and accordingly almost identical to that of teflon. The theoretical delay was 37.5 my secs. With the air gap the experimental delay was 35 my secs. and when immersed in oil the experimental delay was 37.5 mysecs. The oscil- lographs obtained are shown on Fig. 4.11. Due to the agreement between the theoretical and experimental delays when the delay line was immersed in oil clearly the air gaps must have caused the increase in the velocity of propagation. Delay Line No. 2b The 15 inner turns of No. 2a were removed thus making its delay time identical with that of No. 1 so that the effect (if any) of halving the separation distance a between the centre lines of suc- cessive spiral turns could be detected. No observable difference was obtained between the output and that of No. 1 indicating that the effect of halving the dimension a gave no measurable change in the cross st. * Wemceo - c = Insulating oil Page 110 coupling. The noise in the lines (see figure 4.11) could have been due to cross coupling or line imperfections. Another delay line (No. 3) with both ends accessible was tested so that a distinction could be made between cross coupling noise and other noise. Delay Line No. 3 The dimensions of this delay line and the plan view of the centre conductor are shown on figure 4.12. The theoretical charac- teristic impedance of the line was about 30 ohms and was in good agreement with the experimental value. The a/b and a/w ratios were 2.9 and 2 respectively. The schematic circuit layout is shown on figure 4.13 where the end B of the miniature delay line was an open circuit except for the scope probe (4pFarads). The input, reflected and return pulses were detected on channel A and the transmitted pulse (doubled due to the open circuit) was measured on channel B. The return pulse on channel A was virtually unchanged when the scope probe al B was removed thus indicating that the effect of the scope probe at B was negligible. Some of the oscillographs obtained are shown on figures 4.14, Since the measured output on channel B on figures 4.1l4a and 4.14b is zero until the pulse arrives cross coupling cannot have occurred because if it did it would have produced a precursor to the pulse. Hence, the noise must be due to line imperfections and the terminations. As discussed in Part 5 this delay line was later used as a memory device with tunnel diodes connected at both ends. The Selection of the Dilectric Constant Since the previous experiments show good agreement with theory it was decided to investigate the variation of the losses per me secs. with the relative permeability of the insulating material. For simplicity the insulating material was assumed lossless (i.e. tan § = O in eq. 4.1) so that the only losses are copper losses. The second and third columns of table 4.1 show the value of Aas defined in equation 4.1 for two different values of the ratio t/b Page lil (see Fig. 4.2). With tan’ = O equation 4.1 can be rewritten a . x Nikme 5 db/my sec. where A = = and C = velocity of light per my sec. If the dimension b is in metres then A = A/0.3. TABLE 4.1 A ZN kK t/b = 0.01 tib= 0.1 0 . 06039 . 00042 20 00045 . 00046 40 . 00053 . 00051 60 . 00060 . 00055 80 . 00068 . 00060 109 . 00076 . 00066 120 . 00087 . 00074 140 . 00100 . 00086 160 . 00145 . 00103 180 . 00140 . 00135 Hence, for any value of the characteristic impedance (Z) the value of A and accordingly the attenuation per musec. increases as the dilectric constant increases when b and EKMC are fixed. However, the volume per musec. is approximately proportional to 1/Vk and decreases with increasing k. Clearly then there must be a compromise between the losses per myusec. and the volume per mUsec. and since tunnel diode circuits have low gain the value of the dilectric constant should be low except in cases where low volume is of primary importance. If, however, the selection criterion called for minimization of the product of the volume per msec. and the losses in db/my sec. then the minimum value of AW kis required. For any value of Zo Page 112 and for the two values of t/b in Table 4.1 the values of A// k are shown in Table 4. 2 and with this criterion the optimum value of vk Ze is approximately equal to 140. TABLE 4. 2 b and t in meters 10° — VKZ + Ald Joo DLL fe t/b = 0.01 t/b = 0.1 0 “am ~a— 20 7.58 7.66 40 4,40 4,25 60 3.33 3.05 80 2.82 2.52 100 2.55 2.22 120 2.42 2.05 140 2. 38 2.04 160 2.47 2.14 L380 Z.56 2.50 It must be also remembered that materials with higher values of the dilectric are more liable to suffer from one or more of the following defects: (a) High loss tangent (b) The dilectric constant has a higher %variation with frequency. (c) Are more expensive and are not available in sheet form. While the above at least partially justifies the selection of teflon (k = 2.1) as the insulating medium it was decided to build one delay line (No. 4) whose dilectric had a relative permeability of 12. Delay Line’ No. 4 The centre conductor employed in this case was the spiral of delay line No. 1 but Stycast (k = 12) was employed as a dilectric. Two Page 113 30 mill planar slabs of Stycast were cut from a block of the material and the spiral was ctched from a 2 mill copper sheet. The enlarged "tail" of the spiral was removed and a miniature connector” was used to make the connection to the 50 ohm test circuitory. The cxpected values of the characteristic impedance and delay times were 37.5 ohms and 65 mjisecs. respectively but the experimental values were 54 ohms and 50 mysecs. The discrepancy was undoubtedly due to air gaps which reduced the effective value of the relative permeability of the dilectric to about 7.1. With this reduced value the losses per my sec. were not very different to those for the teflon line (0.2 db/mysec. as against 0.23 db/myusec. for teflon) and the volume per my sec. was about 30%greater. Hence, from volume and loss considerations teflon is superior to K 12 Stycast as an insulating material. Some test results are shown on Fig. 4.15. The output pulse had a precursor which must have been due to variation of the dilectric constant with frequency since the a/b ratio of 1.6 is only 20%less than that for delay line No. 3 where no cross coupling was detected. Many constructional difficulties were encountered. The material was not available in laminated form and due to. its extreme hardness the cutting task was difficult. Also an unanticipated reaction occurred between one of the photo etching chemicals” ” and the Stycast. Summary: - With an insulating material whose relative permeability (k) is independent of frequency (e.g. teflon) and an input that has the approx- imate shape of a positive half cycle of a sine wave of frequency f kilomegacycles and is otherwise zero, the output amplitude can be accurately predicted using equation 4.1 provided the attenuation is =10 db. For greater losses the pulse attenuation will be less than that for the corresponding sine wave and the pulse spread becomes * Manufactured by Microdot *« Kodak photo resist developer wks This input pulse will closely correspond to a tunnel diode output when operating in a "return to zero'' system at a frequency of f kilomegacycles. Page 114 significant. When this occurs synchronization by means of phase techniques will be no longer possible so that 10 db is about the upper limit of permissible attenuation. Since this value of the attenuation corresponds to a gain of approximately six in a tunnel diode circuit having one terminated input line and one terminated output line, the permissible losses in miniature transmission lines used as storage elements are compatible with the available gain in the tunnel diode circuits. If the ratios of the characteristic dimensions of the transmission line (i.e. b/w, t/b and a/b of Figure 4.1) always have the same value then except at low frequency the db losses are inversely proportional to b and the volume is proportional to pb’, The net result is accord- ingly a compromise between volume and the maximum permissible length of the line. For a10 db loss a delay time of about 42 mp secs. was obtained with the spiral of Figure 4.9 using teflon as the dilectric. The total volume was about 0.02 cubic inches (volume of enlarged section for connection to coaxial line excluded). For the delay lines constructed with teflon dilectric the experi- mental delay was 93% of the theoretical value except in the case where the delay line was immersed in oil with virtually the same relative permeability as teflon. In the latter case very good agreement was obtained between the experimental and theoretical delays. While the discrepancy could be allowed for in the design it should be remembered that this air gap effect will increase with the dilectric constant of the insulator. As an example the measured delay was only 77% of the theoretical value in delay line No. 4 where the relative permeability of the dilectric was 12. Page 115 ingulation Copper ground planes \ \ ‘ S Se Copper center conductor “~.. Air gap Figure 4.l:- Delay line configuration b enema Pe a v 1€ a i) » SR t=l mill w = 16 mills b= 21 mills a= 100 mills Figure 4. 2:- Dimensions of delay line No. 1 Page 116 Figure 4, 3:- Centre conductor of delay line No. 1 Page 117 ; 50 ohm coaxial By \ Figure 4.4a;- Constructional details of spiral delay line spiral conductor tapered pin “10 mill teflon P P a ae a pots " Figure 4. 4b:+ Section A+A of figure 4. 4a Page 8 1 . 085" eed ‘ Figure 4. 4c:- Section B-B of figure 4. 4a 4 \ 7 , , Spiral of figure 4.3 % O, 133" Figure 4..4d:~ ‘Section C-C of figure 4. 4a Page 120 Signal Generator 60 nsec 50 ohm 6 nsec. Delay Delay Tee Delay Line. || Scales:- Hor. 0.5ns/:cm. Ver. 200mV/cm. S = Output. on Hor. 0.5ns/cem. Ver. 100mV/cm. NB Figure 4.6:- Test circuit and input-output pulses of delay line No. 1 ws 5 Page 121 1 ——— Experimental output ~--- Computed output salized fourier transform Wort 0 2 wi .6 .8 l 1,2 requency in kilomegacycles Figure 4.7%7:- Fourier transforms of input and output pulses for delay line No. 1 and cormputed fourier transform of the output input A mput © i} i i @ an » Zirne 1 e+ 8 \ oA \ 9 t ee t \ / ‘ ‘——~ Input B x 4 Output A Output C | | ® | y Lime = V4 ‘ oa S | " aa . | ._ . “S~ Output B bo ' | 1 | I 1! Combined outputs Sp > Sime iss} + rod ie) = figure 4,8:- Superposition of pulse responses Page 123 Figure 4.9:~ Centre conductor of delay line No. 2 Page 124 WSS a ‘aan Input. Scales:-. Hor. .0.5ns/cm. Ver. 100mV/cm. Output. Scales:- Hor. 0.5ns/cm. Ver. 50mV/cm. Figure 4.10:- Input-Output pulses for delay line No. 2 Page 125 Signal 60nsec. 50 ohm 6nsec. Miniature Generator Delay Tee Delay A Delay Line v to scope Schematic layout of test circuit With air gaps. Input on left obtained by second exposure with open circuit at A Under oil. Scales:- Hor. 5ns/cm. Ver. 200mV/cm. Figure 4.11:- Fiffect of air gaps on velocity of propagation. Page 126 E | t | | | Plane of IK Symmetry | | ! | | | | ' ere 28 mills | | | | eg 1 a 36 i 36 1< mills mills Figure 4.12:- Dimensions of delay line No. 3 Pulse 60ns delay 5ns delay A |Miniature B Generator (50 ohm) (50° ohm) delay line No. 3 To scope To.scope To scope sync. (Channel A) (Channel B) Figure 4.13:- Test circuit for delay line No. 3 Page 127 Channel A Channel B 100mV/cm. (Channel A) 200mV/cem. (Channel B) Figure 4.1l4a:- Pulse response of delay line No. 3 Ver. aa = tens Channel A SaGRe eee... A A Sh di Scales:- Hor. 10ns/cm. 100mV/cm. (Channel A) 200mV/cm. (Channel B) Figure 4.14b:- Pulse response of delay line No. 3 Ver. Page 128 i} | | ani Input pulse (Channel A) ae a Output pulse (Channel B) Return pulse from open circuit at B on Figure 4. 13 (Channel A) Scales:- Hor. Ins/cm. v 100mV/cm. for input and output pulses * 50mV/cm. for return pulse Figure 4.1l4c:- Pulse response of delay line No. 3 Page 129 Input iN Scales:- + Hor. Ins/cm. Zan Ver. 2Z00mV/cm. anngyy anemet Output Scales:- Hor. 2ns/cm. Ver. 100mV/cm. Figure 4.15:- Pulse response of delay line No. 4 Page 130 PART 5 REGISTERS AND MEMORY BHLEMENTS A register or memory element incorporating a miniature delay line and two tunnel diodes was constructed and tested. It was decided to use bidirectional coupling” since this simplified the bias problem by permitting the diodes to be driven by the same clock phase. The configuration selected consisted of delay line No. 3 with a tunnel te sh i ate ste ak diode at each end and a power feed through its mid point as illus- trated in figure 5.1. The configuration was selected because of its basic simplicity and even though it could only hold 12 bits at about 320 megacycles it is nevertheless an extremely practical storage element. Input-output circuitory was excluded, but this could have been added in accordance with the directional connection rules of Essentially, the circuitory was maintained as simple as pos- sible primarily because this simple circuit would provide a good check on the validity of the + parameter when tunnel diode circuits are inte- grated with miniature delay lines and partially because the required power could be easily supplied. Using a sine wave and superimposed D.C. bias giving a total % bias of about 97.5% the circuit operated satisfactorily at its synchro- nous frequencies up to about 500 megacycles. If ‘lis the line delay time (B to A of figure 5.1) and 7,18 the diode delay (ry = time interval between the maxima of the input and output signals) then the synchro- nous frequencies are on n — f° TIF n= 2, 4, 6,. * See section on bi-directional coupling in Part 3. * 20 mA, 10pF tunnel diodes were used (R. C.A. type T.D. 182) ask «=An example of one possible input-output configuration is later given in this section. Page 131 and the number of bits (n) stored in the line increases almost linearly with the synchronous frequency f At the cut off frequency of 500 megacycles the one way attenuation factor in the line (see figures 4.14a and b) is about 2.0. Also the transmission coefficient (t) at C (figure 5.1) is 0.54 for pulses simultaneously emitted from A and B which then intersect at Candis 0.77 for a pulse emitted from A or B when the other remains low. Hence the gains c} are (a) a = 3.7 (pulses crossing over at C) (b) — = 2.6 (pulses which do not ee) over For a gain gi of 3.7 and 97.5%bias figure 2.14c predicts a value of 7 of about 0.6 since the load line corresponded to a value of Eo of about 600 millivolts. The T/C ratio of the tunnel diodes was 2 so that the expected value of f nax from equation 3.13a is about 650 megacycles. This value compares reasonably well with the experi- mental value of 500 megacycles when it is remembered that no allowance was made for the capacity of the scope probes. * With the operating frequency reduced to about 320 megacycles 12 bits of information could be stored in the line. Figure 5.2 shows some oscillographs of the voltages at the points A and B of figure 5.1 at this frequency. The signal to noise ratio is about 20 db. A close inspection of figure 5.2 will show that the pulses which simultaneously originate from the two diodes have a slightly lower amplitude than a pulse that originates from A (say) when B remains low. This is a consequence of the two possible values of the transmission coef- ficient (t) at the point C in figure 5.1. ale os When an allowance is made for the 2pF capacity of the scope probes, and an additional lpF stray capacitance the theoretical fmax is 515 megacycles. Page 132 As anticipated the performance of the circuit was critically dependent on the %bias and drift in the d.c. power supply frequently led to failure of the circuit. Also the diodes had to have their peak currents matched to within 1%. The delay line volume per bits was about 0.06 cubic cms indi- cating that at best 1.3 x 10! bits of information could be stored ina cubic meter. Even if this number would have to be reduced by a factor of 10 to provide ventillation,space for power supply lines etc., a high packing density will still be obtained. Indeed, when there is no necessity to keep volume and weight "to a minimum" it would be possible to increase the linear dimensions of the delay line by a factor of about 2.7 and hence volume by a factor of 30 thus allowing the above circuit to operate at 320 megacycles and hold 32 bits. Longer registers can be obtained by constructing a closed chain of OR gates phased to give directional operation as outlined in Part 3. With the four phase system 4n diodes must be employed where nis any integer. The OR gates would have one input and one output and so with terminated line 8" and the diodes operating with a current gain of 8 an attenuation factor of 4 is permissible in the delay lines. Even if the attenuation factor is only 3 then with a delay line of the ditiuensions and length of No. 4 in Part 4 the number of bits stored in the register would be 48n. It is also feasible to include read, write and other logical clements at any of thesc OR gatcs. Figure 5.3 shows a possible logic configuration where the contests S of the register will be circulated (B low) or inhibited and the input A read in (B high). The circles indicate the tunnel diode positions and the number at the lower left of each circle is the phase number of that diode. The quantities in the circles are the logical outputs of the diodes. All the diodes are positive under biased except the one * Since multiple reflection problems are not severe in this case it is feasible to operate with non terminated lines which essentially daubles the current gain of the diades. Page 133 whose output is the mirror image of the compliment of the input (A). This latter diode is negative overbiased. On the connecting line the numbers k, X or (k, + 1/2) \ indicate the length of the connecting lines where k, is an integer or zero and \ is the wavelength in the dilectric at the synchronous frequency. The total number of bits (N) which can be held in this register is given by the equation N = n(4k, + 1) + 1 + sk. uy Apart from applications to general purpose computers there are equally attractive applications to digital differential analysers and special purpose computers. Essentially the registers or memory elements are equivalent to drum storage when the peripheral velocity of the drum is equal to the velocity of light divided by the square root of the relative perme- ability of the insulator in the delay lines. Finally the tolerances in the line delay times will not lead to cumulative effects since the clock phase will tend to pull the lines into synchronization. A brief investigation with the circuit of figure 5.1 indicated that the line could have a length tolerance of about 1/10 of a wavelength. Consequently if the line length between diodes is nomi- nally 10 wavelengths the permissible tolerance is 41%. Page 134 Delay Line pH» ‘lo Scope Sync. Power Supply Figure 5.l:- Register or memory device Page 135 Voltage at A W Voltage at A Voltage at B Voltage at A Scales:- Hor. 10ns/cm. Ver. 200mV/cm. Figure 5.2:- Output voltages at points A and B of Figure 5.1 Ane-l diodcs 4u delay lines cach of length KO nN “igure 5. 3- Ba ! direction of ' | S ' propagation & “*) \ ‘ { . A Se Ka?) ~futput (5) input (A) Memory elernent with input-output logic Page 137 PART 6 SUMMARY AND CONCLUSIONS This thesis can be divided into two major sections. In the first of these the parameters and parasitics which determine the switching speed of tunnel diode circuits were investigated and a non-linear computer analysis technique applicable to these circuits was developed. In the second section a set of logic elements, a method of connecting these elements and a high speed memory device were developed. The non-linear analysis was performed by means of a special purpose compiler programmed to operate on the Burroughs 220 digital computer. This compiler or circuit analyzer was frequently employed to determine the performance of various circuits and obtain optimum parameter values. Part 1 of the text deals with parameter measurement and justification of the equivalent electrical circuit of the tunnel diode. In Part 2 the quasi-dimensionless parameter 7 was introduced. This parameter is a measure of the switching speed of a tunnel diode and can be employed to predict the maximum permissible repetition rate of a logical circuit. The dependence of r on % bias, circuit gain, load line and parasitic inductance was investigated and some numerical values were obtained for germanium tunnel diodes. Also in Part 2, a complete set of logical elements (the OR, AND and COMPLEMENT gates) was derived from the single diode circuit. This latter circuit operated extremely well as a logical OR gate but it was not directly applicable as a COMPLEMENT gate and did not have sufficient discrimination to satisfactorily perform the AND operation. A modified AND gate design, which has the electrical sensitivity of the OR gate, anda COMPLEMENT circuit arrangement were obtained by means of mixed bias circuitry and an inverting one to one transformer. Page 138 Since the tunnel diode is a two terminal device logical elements must be made directional by some external means. In Part 3 blocking diodes were found to be at best marginally applicable since their capacity removes the major part of the directionality at the high operating frequency. In addition their non-linearity could not be advantageously utilized in the coupling of the mixed bias logic elements of Part 2. A method of direct connection using terminated transmission lines and clock phasing gave good directionality and in addition made the maximum operating frequency dependent only on the tunnel diode parameters and the required circuit gain. Although reasonable fan in and fan out ratios are obtainable this method imposes the necessity of certain connection rules. These connection rules permit a high degree of flexibility but it is probable that complete generality can only be obtained by the introduction of a bit time that is an integral multiple of the A.C. clock period. In Part 4 compact miniature electrical delay lines were discussed and from their measured pulse response and delay times it was concluded that they could be successfully integrated with the tunnel diode logical elements to give low volume high speed memory devices. The upper limit of permissible attenuation in these delay lines was about 10 db at an operating frequency of 400 megacycles since higher values of the attenuation leads to considerable pulse distortion, One such memory device was constructed (report in Parl 5). It had an upper frequency limit of about 500 megacycles and when operating at 320 megacycles it held twelve bits. Its total volume, excluding the volume of the two tunnel diodes, was approximately 0. 75 cubic centimeters. Many problems will be encountered in the construction of complex systems. The apparent limitations resulting from the con- nection rules of Part 3 will demand further efforts in the field of logical design. The maintenance of the necessary fine tolerances not only in the tunnel diodes but also in the resistive elements, power supply voltages and the delay times of the electrical transmission lines will require careful quality control or a method of parameter Page 139 adjustment in constructed circuits. Input-output buffers must be developed and improvements in measuring or detecting devices are desirable since present day sampling oscilloscopes have a rise time about equal to that of tunnel diode circuits and a probe capacity of two picofarads can cause almost a 20% change in the rise time of a ten picofarad tunnel diode, Since these difficulties are predominantly of a technological nature there can be little doubt that the high switching speeds of tunnel diode logic circuits and the availibility of a high speed memory device, which can he integrated with the logical elements, would lead to data processing systems with operational speeds a few orders of magnitude greater than that of those presently available, 7 BP OD AAA Aa w bh KMC max rl Page 140 PARTIAL TABLE OF SYMBOLS Tunnel diode capacity (c = C, except in Part 1 ) Tunnel diode capacity at zero bias Blocking diode capacity Tunnel diode capacity at the valley voltage The directionality factor The bias voltage The Thevenin equivalent bias voltage Frequency in kilomegacycles per second The maximum permissible value of feMC A dimensionless frequency The tunnel diode voltage gain for a single loop (Thevenin equivalent) circuit. The minimum value of G at any load line and percentage bias The maximum value of G at any load line and value of the percentage bias. The maximum value of Gy; at any value of the percentage bias The voltage gain of the circuit The current through the tunnel diode The charging current (I. = {[- 14) The current which maintains constant voltage across the tunnel diode (Voltage dependent). The static value of I when the diode is in the low state The tunnel diode peak current The tunnel diode valley current Relative permeability Page 141 L Total inductance (L = Lian + L,) Lan The lumped inductance of the bias circuit Ls Tunnel diode series inductance m The number of outputs of a logic circuit (fan out) mA Milliamperes mV Millivolts muH Milli-microhenries (ImyH = 10° ’Henries) musecs Milli-microseconds (Impusec = 107? seconds) n The number of inputs to a logic circuit (fan in) nH Nanohenries (1 nH = 107? Henries) ns Nanoseconds (lns = 107? seconds) Pp The power dissipation in a logic element in milliwatts pF Picofarads (i.e. Farads x 10714) R The load line resistance Rn The reciprocal of the slope of the tunnel diode V-I characteristic. Re The series resistance of the tunnel diode Ro The bias resistor Ry The parallel impedance of the input lines in the high state Ro The parallel impedance of the outputs r Resistance terminating a delay line T The clock period vV-i Tunnel diode voltage current characteristic when characteristic the effects of the series resistance Rs are removed Vv The voltage across the capacitor of the tunnel diode equivalent circuit Ve The value of the voltage V when the diode has risen 90% of its total rise N T w % Bias Page 142 The static value of V when the diode is in the low state The static value of V when the diode is in the high state ll I P I v The voltage on the V-I characteristic at I iH The voltage on the V-I characteristic at I The energy gap The load line voltage corresponding to the current I The characteristic impedance of the transmission lines connecting the logic elements The characteristic impedance of the power supply lines Attenuation factor in the transrmissivun lines comuecting the logic elements Dimensionless zero to 90% rise time parameter Angular frequency The % Bias is defined as 100 Iy/Ey: Page 143 REFERENCES Sommers, H. S., Jr. Tunnel diodes as high frequency devices. Proceedings I, R.E,, 47 (July, 1959), pages 1201 - 1206, ’ Arditi, M. Characteristics and Applications for Microwave Wiring, Symposium on Microwave Strip Circuits I.R.E., (March, 1955), pages 31 - 56, Guillemin, E,A. Introductory Circuit Theory Wiley Cooperman, M., Proceedings IEEE, (1963) Pacific Computer Conference, pages 166-186. Cohn, Seymour B. Problems in strip transmission lines, Symposium in Microwave Strip Circuits I. R.E,, (March, 1955), pages 119 - 126. Vou Hippel, A, Dilectric Material and Applications. Wiley pages 331 - 333, 370. Page 144 APPENDIX I PROGRAM TO COMPUTE THE TRANSIENTS IN ELECTRICAL NETWORKS USING THE BURROUGHS 220 COMPUTER by Patrick G. O'Regan ABSTRACT The program will compute the transients in practically all linear networks provided an independent set of loop currents exists such that at most only two currents flow through any element and, if there are two, these currents are flowing in opposite directions. One type of nonlinear element is permitted and that is a nonlinear resistance in parallel with a linear capacitor. TABLE OF CONTENTS Abbreviations Introduction Program Limitations Mathematical Discourse The Input Statement Diode Characteristic Preparation of Data Tape Operating Instructions Error Halts Output Format Page 145 Page 146 147 147 148 152 160 161 162 163 165 ABBREVIATIONS horH Page 146 The integration interval (also called the time interval or step interval) The number of independent current loops in the circuit under consideration The number of co-ordinate points taken on the V-I characteristic of a diode The number of different (non-identical characteristics) diodes in the circuit The number of integration intervals between printouts, [s is stored in 0475 (Relative).] Page 147 INTRODUCTION This program is primarily intended to solve transients in electrical circuits in which diodes, and in particular tunnel diodes, are present but is equally efficient in the case of linear R-L-C net- works. Solution is obtained by means of step-by-step integration using the fourth order Runge-Kutta method. PROGRAM LIMITATIONS l. The electrical circuit must be such that there is an inde- pendent set of loop currents with one or two, but no more than two, currents through any element, and if there are two, these must be flowing in opposite directions. All planar circuits and many non- planar circuits meet this requirement. 2. The loops must be selected so that the following types of loops are prohibited: a. k inductive loops (i.e., an inductance in each loop) where the number of inductors in these loops is less than k. k=2, 3, 4, 5, ... ,n. b. k noninductive loops where the number of resistors in these loops is less thank. k= 2,3,4,5, ...,0n. 3. All the driving sources must be voltages, but current sources may be simulated by means of a high voltage source with a high internal resistance. At present, the voltage sources are limited to step or camp functivus bul may be extended by means of a sub- program. 4. The maximum numbcr of different diodes (nonlinear resistance in parallel with a linear capacitor) is limited to 7, and each loop containing a diode must have an inductance in it. 5. The maximum number of loops is about 25 but is slightly dependent on the input statement. If nis the number of loops, q is the number of non-identical diodes and I is the length of the input statement, then the following inequality must be satisfied: I+ 4n“+ 15n+1374 + 40q <= 5000 (core storage capacity) . Page 148 MATHEMATICAL DISCOURSE Assume that n independent current loops exist for the circuit under consideration and all the conditions imposed in the ''Program Limitations" section are satisfied. Using Kirchhoff's second law, the dynamic equations of the circuit may be written in the following matrix form: [uo] (S)+ [rR] m+evy = ® (1) + ‘dt c where (1) [wu | is the inductance matrix. (2) [R | is the resistance matrix, (3) (2V ) is a vector whose jth component is the sum of the capacitor voltages around the jth loop when traversed in the opposite direction to the assumed direction of flow of the jth current. (4) (E) is the applied voltage vector whose ith component is the applied voltage in the jth loop when traversed in the assumed direction of flow of the jth current. (5) (FS is a vector whose jth element is the rate of change of the i loop current with time. (6) (I) is the current vector whose ith element is the jth loop current. The Inductance and Resistance Matrices The inductance matrix takes the following form: L -L -L a0 a1 0, (n-1) “hig Ly Jt JJ Un-1), (n-1) —i Page 149 where L., is the sum of the inductances in the jth loop and L,. is the inductance common to the jth and jh loops. (L.. = L,.) Yj J The resistance matrix is to resistance as the inductance matrix is to inductance. Solution of the Dynamic Equations Assume, for the purpose of explanation only, that the induc- tance matrix is non-singular. Equation (1) may then be written: (SF) = fey t -[R] tn) -ev.ie I} (2) and so knowing the initial conditions =) may be obtained. The teh once (1), is known where h is the step increment of time. The only difference Runge-Kutta procedure can be employed to obtain (1) between (2) and the customary type of equation is that there is the (2V 0) vector appearing in (2) which is itself time dependent. Suppose then that (SF) can be computed from (2) at time t. Using the Runge-Kutta procedure (ap) must be computed four times in all at times T where r.k. Te. k. t T =t+ h (twice) rok. 2 and Th k. t+h before ey nh iS computed. Thus (=V) is required at The. but only known at.time t. The approximation made is that dzv Vo) = eV) + (Took - t) a 2 cwk. t and so Equation (2) becomes @, = BD { le] o- eva -c.. 9a ey T t o_o t r.k r.k. (3) Page 150 d(2V .) The vector aE may be computed at time t since the loop t th d(2Vv_) currents are known att. Thei element of ap is I. - I'. I. - f. - I'.. i iy i j ij C.. C.. ii : ij where the summation is taken over all j that possess coupling capac- itance with loop i. Here rs and Ie. are the currents through the nonlinear resistors of the diode in loop i and the diode(s) common to loops i and j respectively. For an ideal capacitor I'.= By _ C.. is the capacitance (diode or otherwise) commontothe i” and j loops. C.5 is the capacitance in the ith loop not common to any other loop. Accordingly, using Equation (3) and the Runge-Kutta method, (1) may be computed if (I), is known. t+h t Singular Inductance Matrix The inductance matrix may be singular due to one of the following reasons: (1) No inductance in one or more loops. (2) Less than k inductors in k inductive loops. k=2, 3, ..., n. Case (2) is not admissible by (a) of part 2 of "Program Limitations", In case (1) Equation (1) may be written (when loops are suitably renumbered): L 0 ar’ tk Bx 3k | aE R I pa Vo 7 E Jan ate + ale ate nfs ate + ale ste ~ ate ate 0 | 0 di” R” \\r- a ~ dt Page 151 Differentiating the dynamic equations corresponding to the noninductive loops ana rearranging gives: 0 By (a) and (b) of part 2 of ''Program Limitations", the 'L" matrix of (4) is now nonsingular and so: ate 7 1 ate L 0 R* Sv oe E* dl | = |. - (I) - — + . (4a) seats d ses ad ses R 0 ar =. SE Equation (4a) is now analogous to (2) and so the equivalent equation to (3) is: (Ta 78 oer | + a ee (5) dt r.k. 2 ve The only new term appearing in (5) is (2 =v d it be computed in the same manner as dav except that current dt derivatives are substituted for currents. ste ‘ which may Either Equation (3) or (5) applies to arbitrary circuits satis- fying all the conditions specified in the ''Program Limitation" section. Thus the Runge-Kutta method may be employed to obtain on when conditions are known at time t. It should be remembered that each Page 152 diode must have an inductance in series with it (Program Limitation, part 4)so the second derivative of the voltage across a diode will never be required. Also, it should be noted that the derivative of the applied voltage is required in noninductive loops. Calculation of New Conditions at Time t+h The new conditions are Q) Dy, and, = D+ (AD (6) where AI is computed from (3) or (5) using the Runge-Kutta procedure. (2) The new values of voltages across capacitors from which the new (=V) vector is computed. Vi (tth) = V. (t)+A Vo (7) where I (t+h)+I1 (t) AV -| c ce —_ ~I! MEAN h (8) c 2c c I. (t+h) and T(t) are the capacitor currents at times (tt+th) andt respectively and are known. I'MEAN is the mean current through the nonlinear diode resistance during the time interval h between times t andt+th. I'MEAN = 0 for an ideal capacitor. In the case of a diode, I'MEAN may be obtained to a sufficiently good approximation by the following method: (a) Compute AV. as though I'MEAN = value of I' with the capacitor (diode) voltage equal to V At). (b) Compute I' with capacitor (diode) voltage = V (t+ AV. as obtained from (a). ; (c) Take I'MEAN as the mean of the 2 I'(s) as computed in (a) and (b) and use Equations (8) and (7) to get V (tth). THE INPUT STATEMENT The input statement must define the circuit, the initial con- ditions (currents and capacitor voltages) and the driving voltages, if any. All the currents and capacitor voltages must be specified even though some or all of these may be zero, but only the non-zero driving voltages (non-zero derivatives of driving voltages in cases of non- inductive loops) need to be specified. Page 153 The following hierarchy of codes is used and explained below: (1) 9999 99 9999 This is the END OF INPUT statement. (2) 9999 99 99xx The next word of the input statement is the initial value of Let (3) 9999 99 xxyy The words of the input statement between this code and the next code specify the elements common to loops xx and yy. In this statement xx < yy and xx = yy if elements have only one loop current flowing through them. Immediately following this statement the type of element is specified and 0000 00 0001 classifies a resistor 0000 00 0002 classifies an inductor 0000 00 0003 classifies a capacitor Immediately following the classification word the value of the element (in ohms, henries, or farads) appears and in the case of capacitance its initial voltage (which must be the voltage drop in the direction of I is the next word. Then the next element (also in loops xx and yyjis classified and its value, and initial voltage in case ofa capacitor, is given. Only one of cach Lype of element may be specified. Example: Suppose that I, and rT. flow through a resistance of 20 ohms, an inductance of 10 henries anda capacity of 1.5 10 farads (scaled values) and the capacity initially is charged to 3 volts as shown in sketch below. 20 Ts Page 154 The input statement is 9999 99 0305 (1,-1,) flows in the following elements. 0 02 Inductance follows. 5210 00 0000 Value of inductance. 0 Ol Resistance follows. 5220 00 0000 Value of resistance. 0 03 Capacitor follows. 4815 00 0000 Value of capacitor. 5130 00 0000 Initial voltage. Diode Classification It has been previously stated that 7 different diodes may be used. The word "different'’ here means that the diodes possess characteristic V-I curves that are not identical. Each different diode may be given one of the following numbers: 1, 2, 3, 4, 5, 8, and 9 - and this number is used as a tag to identify the diode. On the input statement the diode is classified as a capacitor except that the sign of the capacitor value bears the tag number associated with that diode. Tag numbers 8 and 9 are to be avoided if possible since there may be lim- ited trouble in reading in 8's and 9's in the sign column. Example: Suppose I, flows through the following circuit: i Diode (Tag 3) Page 155 The input statement is yyg¥9Y 99 O10L1 aT flows in the following elements. 02 Inductance follows. 5160 00 0000 Value of inductance. 03 Capacity follows. 3 4870 00 0000 Diode (Tag. 3) capacitance. -4915 00 0000 INITIAL VOLTAGE (in volts). Alternately it may be stated that an ideal capacitor has a Tag. 0 associated with it. The negative value of the initial voltage across the capacitor in the above example is due to the fact that, in the direction of L; the voltage drop across the capacitor is -15 x 107? volts (-15 millivolts). (4) 9999 90 0000 The words of the input statement between this and the next code specify the value of h (time increment) which may be step- wise time dependent. Suppose the plot of h against time is: ZR aH ee ee t, very large | time Page 156 The input statement is 9999 90 0000 2 J pin floating point form The next input statement (which is 999i ii iiii where i'(s) can have any value) immediately follows h, and is automatically used as 4 7 (5) 9999 00 Opxx The words of the input statement hetween this and the next code relate to the driving voltage in loop XX; i.e., Eyy (the time derivative of driving voltage in loop XX if there is no inductance in this loop) which is classified by p. p=l means Ey is a series of step functions. oA is a combination of step and ramp p=2 means EY Xx functions. If p is not equal to l or 2 a subprogram must be included to compute E The exit to the subprogram is obtained by inserting xXx’ the instruction BUN aaaa (unconditional transfer to location aaaa) into location 0494 (relative to the initial address of the compiler). Exit to location aaaa will occur with the number p in the 4th most significant digit position (sign excluded) of the A register. The time (T will be in location 1222 (relative). The subprogram must rk, return to location 0505 (relative) with Eyy in the A register. Note: - Page 157 p can be replaced by a two digit number in the 7th and 8th most significant positions of the input format and these will be in the 3rd and 4th positions on exit to the subprogram Example 1 Suppose Ey. XX > F&F x has a time variation as shown below. time The input st 9999 te oo atement is 00 OLXX By ; Ost<t + Floating point form Page 158 Note: Att=t,, E = yz ie, 1/2 step. t, is again the next code whichis 999i ii iiii. 4 Example 2 Suppose er has the time variation as shown below. EXx E, Oe eae i | | | Ey time to 4 ts t. ty The input statement is 9999 00 02XX *y lst co-ordinate point on Ey t curve t 0 Ey 2nd co-ordinate point on Evy - t curve 3rd co-ordinate point on Eyy - t curve 4th co-ordinate point on Eyy ~ t curve st cal i.) Page 159 3 5th co-ordinate point on E - t curve XX t. 3 By 6th co-ordinate point on Eyy - t curve b4 Ey } 7th co-ordinate point on Eye ~ t curve There is no need to insert t. since the next word is 999i ii iiii. 5 (6) (a) 9991 00 xxyy This is a print instruction and reads print Lo ty (xx ¢ yy). Ifxx = yy it reads print Loe Note: Only one word is required in the input statement to print the current in any element. (b) 9990 00 xxyy Op Or0v This is also a print instruction and specifies that the total voltage across some or all the elements common to loops xx and yy is to be printed. p= 3 voltage across capacitor (or diode) is included in printout. ra2 voltage across inductance is included in printout. v- 1 voltage across resistor is included in printout. Ifp, r, or v = 0, the corresponding voltage is not included. Example: DO Page 160 Suppose we wish to print: (1) The current I, (2) The current (I, - U) (3) The voltage across Logt Cog The input statement is 9991 00 0000 Print - 9991 00 0001 Print (I, - 1) 9990 00 0000 03 0200 Print voltage across Log and Cog Comment It is not always possible to print the voltage across a resistor. If the L matrix was originally singular the resistance element may have been transferred from the R to the L matrix and the resistance in the R matrix may now be zero. The result is that a voltage may sometimes be printed as a zero when in point of fact this is not so. Printout occurs after every S iterations where S may be preset [s x 107? in location 0475 (Relative) | Concluding Remarks About the Input Slatement The input statement must be read into consecutive locations beginning at 0000. Consequently on tape the input statement should be preceded by a 6 0000 PRB 0000 command and followed by a 6 0000 HALT 0000 command, DIODE CHARACTERISTIC Every diode with a different tag number must have its V-I characteristic specified. A maximum of 20 points on the character- istic may be specified and between consecutive points (consecutive valucs of V) the V-I curve is interpolated as a straight line. The Page 161 voltage coordinates of the m(m<20) points on the characteristic are arranged in the order in which they appear on the real line starting from the left and must be readin. that order into the m consecutive cells beginning at the relative location (a) 1274 + 40 (k-1) where k is the tag number of the diode andk=l, 2, 3, 4, or 5. (b) 1274 +40 (k - 3), k =8o0r9. The corresponding currents must be read into addresses 20 greater than their respective voltages. In tunnel diode circuits a convenient time scaling is to let 1 second computer time be equivalent to 1 mp~esecond real time. The inductance and capacitance is 10? times that of real time and resistance is unchanged. It is, perhaps, simpler to use milliamps and millivolts rather than volts and amps. This has no effect on element values. However, it is important to remember that the V-I diode characteristic must be in a consistent system of units with the driving sources and the initial conditions. PREPARATION OF DATA TAPE Assume m given points (Vv. 3 I ) have been selected from the diode characteristic and the diode has tag k where 1120, i=l, 2, 3, ..., m, and Vial) > V5 The data tape is 1274+40(k-1), k=1, 2...5. 6 FRB aaaa aaaa -| 1274+ 40(k-3), k= 8, 9. Vv + 1 V2 V3 In fl i i > r n floating point form Vv Page 162 6 FRB {aaaa +20) L \ In ts ? In floating point form tm J 6 0000 HALT 0000 The above input must be repeated for every different diode ex- cept that the 6 0000 HALT 0000 need not be included until all the data has been read in. OPERATING INSTRUCTIONS The program tape may be read into any location aaaa such that I+ aaaa + 4n” +15n +1274 + 40g <5000 and aaaa> I where n is the number of loops, lis the length of the input statement, and q is the number of different diodes. Having decided on aaaa the procedure is: (1) Set the B-Register to aaaa and start read in of program tape with a PRB 0000 command. Following the read in of the program tape, a sum check routine is read into location 4981 to 4997 and this routine is immediately executed. The computer then halts with one of the following commands in the C-Register: (a) The command 0000 HALT 0000 (b) The command 0000 HALT 5555 This indicated a read in error or an error on the tape. The error, Modl, is in the A-Register. Page 163 (2) If the computer halts on (a) above, read in the input state- ment tape and the data tape (s). The input statement tape goes into 0000 and up. (3) Using the keyboard, key into location 0910 (Relative) of the program the maximum allowable diode voltage. (4) The print out routine will be executed after every S steps where (S - 1) x 107 ° is in location 0475 (Relative). Sis set =10 on readin. Change S if necessary. (5) Transfer control to 0000 (Relative). (6) In case of computer halt, consult the section on error halts below. (7) The time increment (h) may be altered if desired in the following way: (a) Set the S register to 0476 (Relative). (b) Set S to P switch on and when computer halts change the input statement so that new h will be obtained. (c) Depress start switch. (8) By the same process as in (7) applied voltages may be changed at any time. (9) The program may be stopped at any time and started over again with new circuit parameters, etc. in the following way: (a) Press clear. (b) Make necessary changes to the input statement and/or the diode characteristics. (c) Operate as indicated in (3) and up. ( No need to execute (3) or (4) unless there is a change in the maximum diode voltage or in the number of iterations between print outs | . ERROR HALTS (1) Halt on the command HALT 0000 after printing one word. The word printed is an error in the input statement and the B-Register contains the address of the error. Page 164 (2) Overflow halt with the P-Register set to aaaa where 9/15 < aaaa < 1155 (relative). Failure is due to either (a) Part 2 of program limitations not satisfied. (b) Error in the input statement. (c) The matrix ste fe is povrly couditioued. (3) Halt on command HALT 3333 This means that a diode voltage has gone below the minimum value specificd by its characteristic. The A-Registcr contains the voltage across this diode and the B-Register setting deterimines the tag- number of the diode. B Register Tag Number 0000 0040 0080 0120 0160 0200 0240 oOo wou Pw nN (4) Halt on the command HALT 0240 This means a diode voltage is greater than the maximum specified by its charactcristic. Again the A-Register contains the voltage and the diode tag number may be obtained as in (3). Page 165 Procedure Following an Error Halt In cases (1) and (2) the error must be corrected and the program may be again entered at 0000 (Relative). In cases (3) and (4) the error is due to either (a) The iterative procedure is unstable due to a too large h. In this case change h in the input statement and re-enter program at 0000 (Relative). (b) An error in the diode characteristic or that step 3 of "Operating Instructions" was not correctly performed. When error has been located and corrected, re-enter program at 0000 (Relative). (c) An error in the input statement. OUTPUT FORMAT The output will be those voltages and currents as specified by the input statement. Their initial values and their values after every s steps will be printed. The print out will occur in the order in which they are requested in the input statement and will be always preceded by the values of time (T) and time increment h. In cases of apparent error in print out, see 'Comment! under 6{b) of the "Input Statement".