anaLOG: A functional Simulator for VLSI Neural Systems Citation Lazzaro, John Paul (1986) anaLOG: A functional Simulator for VLSI Neural Systems. Master's thesis, California Institute of Technology. doi:10.7907/af3r-e056. https://resolver.caltech.edu/CaltechTHESIS:04112012-092513753 Abstract No abstract. Item Type: Thesis (Master's thesis) Subject Keywords: Computer Science Degree Grantor: California Institute of Technology Division: Engineering and Applied Science Major Option: Computer Science Thesis Availability: Public (worldwide access) Research Advisor(s): Mead, Carver Thesis Committee: Unknown, Unknown Defense Date: 1 January 1986 Other Numbering System: Other Numbering System Name Other Numbering System ID UNSPECIFIED 5229:TR:86 Record Number: CaltechTHESIS:04112012-092513753 Persistent URL: https://resolver.caltech.edu/CaltechTHESIS:04112012-092513753 DOI: 10.7907/af3r-e056 Default Usage Policy: No commercial reproduction, distribution, display or performance rights in this work are provided. ID Code: 6906 Collection: CaltechTHESIS Deposited By: Benjamin Perez Deposited On: 11 Apr 2012 16:50 Last Modified: 27 Aug 2024 22:27 Thesis Files Preview PDF - Final Version See Usage Policy. 2MB Repository Staff Only: item control page

anaLoc: A Functional Simulator for VLSI Neural Systems John Paul Lazzaro Computer Science Department California Institute of Technology 5229:TR:86 anaLOG: A Functional Simulator for VLSI Neural Systems by John Paul Lazzaro In Partial Fulfillment of the Requirements for the Degree of Master of Science Computer Science Department Technical Report Number 5229:TR:86 California Institute of Technology Pasadena, California 1986 This work supported by the System Development Foundation ©1986 John Paul Lazzaro Acknowledgements Carver Mead, my thesis advisor, deserves special praise for his trusting and generous support of the anaLOG project. Working with David Gillespie, my re- search partner, has been a rewarding experience. My undergraduate advisor, Paul Mueller, and my mother, Marie Lazzaro, are continuing sources of guidance in my life. Significant contributions to the anaLOG project were made by Mark Bell, Jerry Burch, Lyn Dupré, Professor Joel Franklin, Andy Fyfe, Glenn Gribble, Scott Hemphill, Calvin Jackson, Dick Lyon, Mary Ann Maher, John Platt, and the stu- dents of the C5182 class at Caltech, 1985-1986. This thesis is dedicated to Nancy Lee Henderson. This work supported by the System Development Foundation. Table of Contents . ana + LOG =anaLOG .......... 0... 0. cee eee l.l Introduction ........... 0.0. cee ee ee ee ee eee ee 1.2 The LOG Environment ........0..000 00.0000. eee eeae 1.3 An Overview of Ana ..........0..0... 00.0000 0002 ae . The Mathematics of Ana ............ 0.000000 cee eee 2.1 Introduction ......... 0... 000000 eee eee eee eee 2.2 Solving the System of Differential Equations ......... Se eae 2.3 Solving the System of Nonlinear Difference Equations ......... 2.4 Solving the System of Linear Equations ...............04. 2.5 Completing the Algorithm ...................0..0..0040. . Properties of the Mathematics of Ana ................... 3.1 Introduction .........0.0..0.0 02.0000 0000. eee eee eee 3.2 Evaluating the Stability of the Backward Euler Method ........ 3.3 Accuracy and Complexity of the Backward Euler Method ...... 3.4 The Condition for Convergence of the Newton—Raphson Method .. 3.5 The Rate of Convergence of the Newton—Raphson Method ...... 3.6 Properties of the Method of Leading Coefficients . Simulating a Changing System .....................0000. 4.1 Introduction ...........20.020202.0200.0000.0.0.0..20.. 4.2 Evolving the State of aSystem ............. 0.000000 cae 4.3 Criterion for Simulating a System ................0.000004 . The Modeling Style of Ana ............ 0000.00. 5.1 Introduction 2.2... . ee eee ae 5.2 The Symbolic Evaluation of Partial Derivatives ............. 5.3 Modeling Decisions with Fermi Functions ................. 5.4 Behavioral Modeling for a Robust Simulation .............. . The MOS Transistor ............. 0.0. cee eee eee eee 6.1 Introduction ... 2.0.0.0. 00. ee ee ee 6.2 A Simplified Noulinear Curreut Source 2.0... ee ee 6.3 Output Impedance Extension .........0 20.0.0... eee eee eee 6.4 Completing the Model ... 0... 0.0... cee ee ens 7. The Transconductance Amplifier ...........2.22.......... 30 7.1 Introduction 2... .. ee ee eee eae 30 7.2 Basic Amplification Function .................0000 cae 30 7.3 Computing the Scaling Current .............0.0000-000- 32 7.4 Computing the Output Impedance ...................... 32 7.5 Output Voltage Constraints ........................0.0. 33 7.6 Completing the Model ........0.0.. 0.000000 0. ce eee eee 33 7.7 The Wide-Range Transconductance Amplifier .............. 34 8. Rectification Circuits ........0.0. 0.0.0.0 00 eee ee eee eee 39 8.1 Introduction 2... 0... ee ee eee ees 39 8.2 Basic Rectification Function ..............00 00.00 ee eae 39 8.3 Oulpul Vollage Constraints ..............0200...000000. 41 8.4 Completing the Model ............0....0 0.0.00 0002005 41 9. The Horizontal Resistor Circuil ..........20...........0.. 43 9.1 Introduction 2.0.0... ... ee ee eee ee eae 43 9.2 Basic Resistance Function ............. 00000 cee eens 43 9.3 Definition of Control Currents .......0.......... 00.0000. 45 9.4 Completing the Model ................0....00.000005 46 10. The Ganglion Circuit ..........0. 0.0.00... cece ee ens 48 10.1 Introduction ............0.0.0 00000000000. eee eee eee 48 10.2 Principles of Circuit Operation ................. 000000 48 10.38 The Ana Model ......... 0... 0000. e eee eee eee eee 50 11. Topics for Further Research ................... 0000000 54 Bibliography ... 0... 00... ee ee eee ee eens 56 Chapter 1 ana + LOG = anaLOG 1.1 Introduction The emergence of a very-large-scale-integration (VLSI) design style for analog systems holds unique simulation challenges. In digital VLSI design, analog circuit simulators are used for the electrical verification of small circuit sections with high accuracy. The discrete nature of these systems permits the use of abstract switching models for the analysis of macroscopic logic and timing behavior. This is indeed for- tunate, as a circuit simulation of a VLSI system using a traditional analog simulator is computationally impractical. Analog VLSI design requires simulation tools that concentrate on the functional performance of an analog system, as opposed to a fully accurate electrical character- ization, to verify correct behavior more efficiently. Such a simulator requires models that capture the functional essence of analog circuit primitives in a computationally simple manner. In addition, the structure of an analog design needs to be exploited by creating abstractions of circuit building blocks, rather than simulating circuits with their primitive description. This approach ultimately results in a hierarchical description of a large analog system, which can be simulated at different levels of abstraction, trading off accuracy and efficiency. The higher-level descriptions may be correct for only certain regions of operation, with range checking to indicate improper usage. Finally, the numerical methods used to simulate the description must reflect the unique requirements of functional simulation. By using these tech- niques, a simulation tool tailored to the verification of analog VLSI systems may be developed for a workstation environment. The analog VLSI design style is directed toward system designers, as opposed to integrated circuit engineers. A successful analog VLSI designer must develop an intuition for parallel analog computation, as a digital VLSI system designer needs to develop skills in digital logic and circuit design. The user interface of a traditional circuit simulator, however, is directed toward an cxpcricnced electrical engineer, being batch mode (with textual input and output), unforgiving to the novice user, and isolated from other VLSI design tools. Clearly, the user interface of a analog VLSI simulation tool needs to be made more sympathetic aud educational lo a perspective designer from a nonengineering background. A better simulation user interface portrays the metaphor of an electrical engi- neering lab bench. Using a bit-mapped display and a pointing device, the user can draw circuits in a schematic editing environment. As the circuit is being drawn, however, it is also being simulated, hecause a circuit under construction on a lah bench is always in operation. Symbolic multimeters and oscilloscope probes are available for the display of the ongoing simulation. Schematic voltage and current sources provide system input, with user control of the excitation, and graphical in- dication of source overload. The functional simulator, rather than standing alone, 1 shares the lab bench with tools for documentation, integrated circuit mask design and verification, and other simulators. LOG, an interactive graphical environment capable of hosting tools for simu- lation, documentation, and integrated circuit layout, has been developed by David Gillespie at Caltech. This thesis describes an analog functional simulator, Ana, which includes functional models for a standard cell library of analog computation building blocks designed by Carver Mead. Ana, LOG, the standard cell library, and a graphical layout editor form the basis of a design system used in the analog inte- grated circuits course at Caltech. The remainder of this chapter is an introduction to the LOG environment, and to the Ana simulator. 1.2 The LOG Environment The LOG operating system provides a natural framework in which to manipu- late systems describable as a list of interconnected objects with a static number of ports. The system includes a schematic editor, using a bit-mapped graphics screen and a pointing device, and an object-oriented interface mechanism for external pro- grams. This mechanism allows full integration of tools for simulation, design, and documentation into LOG without source-code access; it functions as a software bus for a set of interrelated programs. The user creates systems in LOG by graphically interconnecting objects, called gates. Gates are not dynamically definable; they are selected from a predefined catalog. Their definition can include an association with a tool; a gate thus can possess type. Each port of a gate, called a pin, also can be typed. When the user creates an instance of a gate, a node for each pin is created and is added to a global node list. The node assumes the type of the associated pin. The user edits the data structure by connecting pins together with wires; redundant nodes are eliminated from the node list during editing. The pins of a gate always are cognizant of their respective nodes. Type checking by LOG ensures nodes of different types can never be merged; type casting is available for exceptions. The LOG interface mechanism for external programs is based on message pass- ing. A tool has an interest in gates and nodes of its type. LOG sends messages to a tool concerning the definition, creation, manipulation, and deletion of these structures. LOG also sends general messages to a tool, such as “scnd debugging information about your tool.” A tool is given access to the entire LOG data struc- ture while responding to a message, with the understanding that only tool-specific sections may be modified. LOG also provides a procedure library tu support data structure manipulation and the user interface. Simulators are tools that predict the transient behavior of a system. Whereas most tools share only the LOG data structures, simulators share two dimensions of time. Because simulation and editing should appear to be simultaneous to the user, each simulator shares CPU time with other simulators and LOG. Multiple to simulators may be used together to predict the behavior of a mixed type system; LOG manages simulation time as a global resource. A simulator can respond quickly to most messages, allowing LOG to maintain a responsive graphical editing environment. Computationally intensive messages specify a maximum response time constraint; a simulator polices itself. LOG adjusts this tzme-slice according to user input activity, allowing transparent switches be- tween a high-performance simulation environment and a crisp editing environment. Timed messages have protocols concerning the noncompletion of the message. The management of simulation time is more complex. LOG begins with simula- tion time reset to zero; the user may also reset the system. During reset, a message sent to each simulator requests initialization of the system state. LOG and the user can request resct, but only simulators can advance simulation time and state. LOG regulates the simulation through several messages. The pass message asks a simulator to compute an advance of simulation time and state for its system. The data structure may not have remained constant since the last pass message, but all pertinent changes have been reported to the simulator. A simulator cannot veto a data structure change or reset simulated time; it must contend with a dynamic system. A simulator reports whether time and state were successfully advanced as it returns from the pass message; an unsuccessful pass either implies that more CPU time is needed for simulation, or that the present data structure is not suitable for simulation. A simulator advances the state of its own system; simulation time is shared by all simulators and must be managed globally. LOG allows all simulators to attempt advancing time; the smallest increase is accepted by LOG, while simulators bidding larger steps are requested to simulate up to the accepted time step. The tstep message informs a simulator of the status of its bid. After a uniform time advance, the simulators update internal system state in lockstep. 1.8 An Overview of Ana A central aspect of an ideal analog VLSI simulation environment is the simul- taneous editing and simulation of a system. The LOG operating system provides an excellent framework for this environment, offering a schematic editor with data structures appropriate for simulators, a communication system that informs tools of relevant system changes in an abstract manner, support for multitasking and multiple simulators, and the global management of a graphical user interface. The design of an analog simulation tool portraying the lab-bench metaphor in LOG raises several challenging issues. In LOG’s multitasking protocol, a tool must control its maximum response time to a simulation message. Constructing the simulation algorithm as a collection of distinct, computationally simple tasks is a method of response-time regulation. The Wessage response can be considered a finite-state machine, executing each task in proper sequence until the allotted time has been exhausted, then saving the present position for a future message receipt. A LOG simulator must contend with preserving the state of an incrementally changing system. In Ana, each piu of a gale has a small parasitic capacitance. When a gate is created, the parasitic capacitors are initialized. During the course of a simulation, these capacitors contain the complete state of the gate. When the data structure is changed, Ana uses this redundant information to evolve faithfully the state of the modified system from the original, presenting an illusion of continuous simulation. System state also can be reset to preset values by the user. Ana attempts simulation only if every pin of each gate of a system is connected to some other pin, excepting measurement gates. A system of this nature is defined as complete. As a result, minor changes can be made transparently, but simula tion stops during major editing, preserving system state and avoiding numerical instability. The lab-bench metaphor demands robust simulation, as nature always finds the fixed point! The “soft” circuit modeling style of Ana promotes robustness. All excitation sources have output impedance and overload limiting. A capacitive path fully couples all pins of a gate to each other and to ground, and all active outputs posses DC impedance. Power and ground, the sole “hard” signal sources, are syntactically checked for shorts. Soft modeling allows a system to absorb abrupt changes gracefully. The mathematical modeling style of Ana also contributes to its stable character- istics. All functions used in gale description are continuous with fully defined first derivatives throughout their range. The numerical methods in Ana use symbolic derivates, not finite differences. The avoidance of gross roundoff errors, and the use of functions with defined derivates, both increase stability. An adaptive implementation of backward Euler integration is used in Ana. A full description and analysis of the method is given in Chapter 2 and Chapter 3. The implementation offers robust performance, with medium accuracy and com- putational simplicity. A noniterative equation solver, special methods for evolving the state of a dynamic data structure, and adaptive relaxation of accuracy during difficulty also aid convergence. The responsiveness and flexibility of the LOG user interface must also extend to simulation tools. Ana can simulate a screen-sized system with sufficient speed for an interactive session. A hierarchical modeling system drives this performance; the library contains concise models for many common circuits. The simple, adaptive integration method also contributes to efficiency. Equally important to user productivity is the leverage of the Ana user inter- face. Visual simulation feedback allows tle quick correction of schematic entry errors; model parameters and system state can be changed with a single keystroke. Schematic multimeters can be added to display results; the simulator easily inter- faces to oscilloscope and plotting tools for graphical output. The pointing device can become a status “probe” to scan the system quickly, and schematic wires can “glow” in various colors to show state. Many gates have warning displays to relate abnormal conditions; sources have “switches” to vary excitation. All these features can be activated without stopping the simulation. Chapter 2 The Mathematics Of Ana 2.1 Introduction In the LOG data structure, a system is described as a list of nodes N1,...,Np and a list of gates G;,...,G,. A gate has an arbitrary number of pins, p. Each pin is connected to exactly one node. For a gate G; with pins numbered 1,...,1,...,p, the node of pin / is given by the function Node(i). The current global simulation time is defined as ¢. Ana views this system as a lumped electrical circuit. There is a voltage potential V; between each node N; and a common reference. The behavior of a gate G; is defined as a set of functions P*,..., P}, sang Pk , where 2 dV Node(1 dV Nod PF = PF (Vii see VNode(p)» et, sas 77 ele) rt is the current out of Node(i) contributed by pin / of gate Gx. By Kirchoff’s current law, the sum of all the current out of a node must equal zero. The system of differential equations (Vise Vases — tl = SS Ph=0 l<i<n : a” det dt all Cy Node(l)=t fully describes the original lumped-circuit system. Ana numerically solves these equations to obtain simulation results. 2.2 Solving the System of Differential Equations Ana first converts this system of differential equations into a system of difference equations. The system variables Vj,...,V, are thus transformed from continuous to discrete; V; is now defined at a specific time tz and is notated Vir. Ana requires its numerical methods to be highly robust, with medium accuracy and good effi- ciency. It is shown in Chapter 3 that the backward Euler method [1] meets these requirements. This method converts the differential equation dV “=f (Vit W =H (V2) into the difference equation tet At — Vrez Ap A (VTA te + At), 6 where the timestep At is the distance between each discrete time value. Using this method, the system of differential equations . dV; av, Bs (Vise Var Be 77 1) =0 l<i<n is transformed into the system of difference equations 7 tz+At tz+At Bi( ve penny VET 5 VietAt _ Vie V,tetAt _ Viz ) Al pees Ap ite + At) =0 l<i<n. It is simple and convenient to derive a new system F = F, where A Fy (Vir). Var Vrs. Wart At AL te + At) =0 LSisn., Ana solves this system of difference equations to simulate the electrical system. Wheu the simulation begins, tz = ¢), and Vie, ...,V,'’ are the initial conditions of the former differential equation. Algorithms for setting initial conditions correctly, and for choosing a suitable At throughout a simulation, are shown in Section 2.5. 2.3 Solving the System of Nonlinear Difference Equations At time tz of a simulation, the present state Vi*, ...,V,# is known. After an appropriate Az is chosen, Vietat, teey Viet At are the only remaining unknown vari- ables. J° becomes the system of nonlinear algebraic equations F; (v1,...,0n) = F; (VirtAt vietat) =0 l<i<n. The Newton—Raphson method [2] can be used to transform this nonlinear algebraic system into a linear one. Given an approximate solution vj’,...,v”, the method produces a better approximation vj’'',...,v@t1, where vt! = vy + 6;. It requires the existence of a good initial guess of the solution v°,...,v° ; Ana chooses v? = V. § & 1? on a a By expanding the system F (v}? + 6,...,v” + 6,) by Taylor’s theorem and keeping only first-order terms, a system of of linear algebraic equations OF; Ov, w OF, Fy (v?,..- uP) 4+ & av nt +...4+ 8 =0 1l<i<n is produced. Solving this system yields 6,,...,6,, and ultimately the improved approximation opt ..,v¥t1_ This process is iterated until a sufficiently close approximation is achieved; later sections include an analysis of the convergence properties of this method, and the establishment of a termination criterion. 7 2.4 Solving the System of Linear Equations The n x n linear equation system produced by the Newton—Raphson method is usually sparse, because typical electrical circuils are sparsely connected. Sparse equation solution methods are more efficient than general techniques, but they are more complex to implement. In addition, sparse methods are iterative in nature; a robust implementation requires additional complexity. The current prototype of Ana uses a general noniterative solution method, the method of division by leading coefficients [2]. OF, Using the notation a, = aon wei = —F;(v/,...,v0”) the system of linear equations F can be rewritten as 0715, +... + Gindyn = 5; 1l<i<n. To solve for 6,,...,5,, each nonzero leading coefficient @,1 is first normalized. The equation with the former a,, of largest absolute magnitude, called the pivot equation, is then subtracted from all others, reducing the n x n system to a (n — 1) x (n — 1) system. This prucedure is repeated until a single equation in one unknown remains. All 6; can then be obtained by direct substitution. A division by zero during calculation indicates a singular system. 2.5 Completing the Algorithm The previous presentation leaves many details unspecified. The selection of a proper At for the backward Euler method, the iteration termination criterion for the Newton—Raphson method, and the correct response to a singular system by the linear equation solver are all unaddressed. In Ana, an adaptive control system is used to resolve these issues and complete the simulation algorithm. In the following discussion, all symbols in calligraphic type are user-accessible simulation parameters. A singular system of linear equations has no solution. A nonsingular system of linear equations may not be numerically solvable, as a result of accumulated roundoff error during calculation. If a system of equations cannot be solved, the Boolean function singular is true. The termination criterion for the Newton—Raphson method compares two suc- cessive approximate solutions of the nonlinear system. A relative comparison must be augmented by an absolute comparison to accommodate solutions of small mag- nitude without roundoff error. Ana considers a system solved at the end of iteration w, if for every 7, either the relative condition or the absolute condition |vj’| < A is met, where R is the relative accuracy and A is the absolute accuracy. If this condition is met, the Boolean function converged is true. If the initial guess of the solution v?,...,v2 is not sufficiently close to the actual solution, Newton—Raphson may diverge. M, the maximum number of iterations, is a system variable under adaptive control. If the algorithm does not converge after M iterations, it probably never converges. If this condition holds, the Boolean function toomany is true. Once a solution has been obtained, the error of the backward Euler method can be checked. The larger the voltage change for a timestep, the larger the approxi- mation error. Ana accepts a solution Vitae, wee »V,fetAt if for every 2, |VietAe _ ve < C, where C is the maximum permissible voltage change for a timestep. If this condition is false, but At< 5S, where $ is the smallest reasonable timestep, Ana still accepts the solution. This condition sacrifices accuracy for a robust simulation during difficult transitions; in practice, it is almost always invoked immediately after a data-structure change. If a solution is not accepted, the Boolean function toobig is true. The choice of an improper timestep may result in a solution Vietat wang Viet At that is physically impossible. Ana accepts a solution only if for all <, c < Vietat < M where £ and ¥ are the lowest and highest plausible voltages respectively. If a solution is rejected, the Boolean function overflow is true. An appropriately small At ensures an accurate simulation. A At smaller than necessary is inadvisable, as it needlessly increases computational cost. Q is the range of efficient solutions. If for all 7 tztAt tz C the present At is inefficient, and in future simulation should be increased. The Boolean function toosmall is true if the current timestep is suboptimal. The adaptive algorithm uses the previous Boolean definitions to control the sim- ulation and update the variables At and M. At the end of every iteration w, Boolean conditions for accepting the present result and halting the simulation attempt are checked. If these conditions are both false, another iteration is performed. If the Boolean condition singular or toomany or overflow is true, the simulation attempted has failed, due to an equation singularity, a nonconverging system, or a 9 physically impossible result. The timestep At is reduced by the timestep divisor D. The simulation is halted, and a new attempt to simulate the system begins. If the condition converged and not toobig is true, Newton—Raphson has con- verged with a solution of desired accuracy, and the simulation result is accepted. If toosmall is true, At is unnecessarily small, and is increased by a factor D. If At grows arbitrarily large, the simulator becomes unresponsive to sudden excitation. ‘lo prevent this condition, At is bounded by the maximum timestep T. Conver- gence was achieved in w iterations; if the next simulation attempt does not converge in J xX w iterations, where I is the iteration factor, an improper At was chosen. Thus M is assigned the value J x w, and a new simulation attempt begins. In many cases, Ana is used to find the DC fixed point of a system, and the simulation accuracy is irrelevant. In this casc, the same control system is used, but toobig always returns false, and toosmall is always returns true. 10 Chapter 3 Properties of the Mathematics of Ana 3.1 Introduction When choosing a numerical method for a particular application, robustness, computational complexity, and accuracy are three major considerations. The per- formance requirements of Ana, detailed in Chapter 1, clearly address these three is- sues. A robust simulation algorithm is essential to portray the lab-bench metaphor. In addition, computationally simple numerical methods are necessary for interactive response. Finally, since Ana is a functional simulator, highly accurate results are not needed. In this chapter, properties of the numerical methods used in Ana-are compared with these desired characteristics. 3.2 Evaluating the Stability of the Backward Euler Method The behavior of a linear resistor 2 and capacitor C connected in parallel can be described by the differential equation dV 1 — = -=—V =-Xr’V dt RC where V is the voltage across the components. The analytical solution of this equation is V (t) = V, exp (—A (t — t,)) , where ¢, and V, are initial conditions. To analyze the stability of a numerical method for solving differential equations [1], it is interesting to compare its result for this problem with the correct solution V(t). Recall that the backward Euler method converts the differential equation dV —-=f(Vt into the difference equation ViztAt _ Viz a =f (viet! t, + At) . Applying this method to the test problem yields, after algebraic manipulation, the ratio yre +At 1 Vie 1+At In contrast, the analytic solution to this test problem produces the ratio VietAt — exp(—A(t + At)) Viz exp(—At) exp(-AAt) = Xa(AAY) = Xn(AAt). 11 Note that X,(0) = Xn(0) and X.(oo) = X,(0oo). In addition, the error function E(AAt) = |Xq(AAt) — X,(AAt)| is bounded for all 0 < AA < oo. A numerical method is called A-stable if its solution to the test problem has these desirable properties. For an A-stable method, the choice of a timestep At affects only the accuracy, not the stability, of the test-problem solution. This test problem is relevant to circuit simulation for several reasons. A typical analog system may have many RC subcircuits. At a specific time in the simulation, however, only a few of these subcircuits significantly affect system performance. An A-stable method allows an appropriate At to be chosen to track the significant subcircuits; a method that is not A-stable may require that a smaller timestep be chosen simply to ensure robust operation. In addition, note that any nonlinear differential equation dV anal (V,t) may be approximated by the Taylor expansion dV of of a av Y —Vo) + ra — to) + f (Vo, to). Over a small interval (¢,,¢, + At), oe can be approximated by At, yielding dV dt — The term F(V,,t,) rarely affects stability. Therefore, the behavior of a numeri- cal method on the test problem can indicate its stability when solving arbitrary nonlinear differential equations. At(V —V,) + F (Vosto) « 3.3. Accuracy and Complexity of the Backward Euler Method The definition of the backward Euler method may be rewritten as [1] vietAt _yte _ arf (VirtAt ¢, + At) =0. If the numerical method is exact, the function D(tz, At) = V(t, + At) — V(t) — Atf (V (tz + At) ,t, + At) is equal to zero, where V() is the true solution of the differential equation. The function D(t,, At), called the local truncation error, is a measure of the error of a numerical method. Replacing V (tz + At) in the definition of D(t,, At) by the Taylor series expansion dV(tz) | (At)? d’V(t,) ry dt? V(t. + At) =V(t,) + At 12 yields the expression (At)? d?V (tz) Therefore, the local truncation error of the backward Euler method is O((At)?). The order of the local truncation error indicates the size of At necessary to achieve a certain accuracy, and thus is an indication of the computational complexity of the numerical method. Most simple numerical methods of higher order than is the backward Euler method are not A-stable, and therefore are unsuitable for use in Ana. 3.4 The Condition for Convergence of the Newton—Raphson Method Given an approximate solution v™ of the nonlinear algebraic equation f(v) = 0, the Newton—Raphson method produces a better approximation w+l_ iw f(v”) — w v =v ~ Fwy = Fl ) as described Chapter 2. This iterative process continues until a sufficiently accurate solution is obtained, as measured by the error function E(w) = |v¥t! — vY|. For robust operation, each successive iteration must produce a smaller E(w). The condition for convergence is shown below [2]. For the correct solution v*, the equation v° = $(v‘) clearly holds, if f (v°) 4 0. Subtracting this equation from the iteration equation v’t! = ¢(v”) gives the expression vo —v%tl = d(v°) — d(v”). By the mean value theorem, the right side of the equation can be rewritten as G(v°) — dv”) = (ve —o)S(E") ow SEM <0, Substitution yields the expression ye — yuri _— (v° _ v”)$ (€”). The condition of convergence for iteration n — 1 is obtained by multiplying together instances of this equation for 0 < w < n—1, which produces, after algebraic manipulation, the expression vi —v™ = (vo — 09d (6) 9 (Ed (EP). Note if le’ (v)| <1 throughout the range (v°, v°), this equation can be rewritten as c Ju® — v™| = jue — vl”, 13 where m <1. In this event, the error |v° — v™| — 0 as n — oo, and the process converges. This condition can be easily expressed in terms of the initial function f(v). Recalling the definition of ¢, oy - £(,_ fe) _ fF") b= 5 (Fey) = Pee Thus, for the convergence condition |¢ (v)| < 1 to be true in the neighborhood of the initial guess v°, the inequality If(w) Ff (v)| < [f (v°)? must hold. Note that, if v° is sufficiently close to the correct solution v°, f(v°) > 0 and the inequality is valid, if f (v°) %# 0. Thus, the practical condition for con- vergence is the presence of a good initial guess v°. This analysis is invalid if f is discontinuous, because the mean value theorem does not hold over the entire range of the function. 3.5 The Rate of Convergence of the Newton—Raphson Method The rate of convergence of an iterative algorithm is a measure of its computa- tional cost as a function of solution accuracy. This measure is easily derived for the Newton—Raphson method [3]. If the solution of the nonlinear algebraic equation f(v) =0 is v’, an approximate solution v” can be written as v°+.,,. The iteration equation yeti = ay F(v™) f'(v) can therefore be rewritten as (vo + €w) €wtl = €w — f'(ve + ey)" The Taylor series expansions of f and f around v° are , Pz uN fv’ + €w) = ewf (v*) + of (v°) ++-- f (v° 4 éw) _ f (v’) + éwf (v°) eee Using these expansions, the expression cuf (9) + $F") + FW) + wf G4) Fo Ewtl = €w — 14 is obtained, which after simplification yields 2 éwf (v°) + ef" (v°) a éwf (v°) _ & f" (v°) eee J'(v°) + wf" (v2) +--- , Cw+1 = Truncating higher-order terms gives the final approximation nN Ew-+1 © fot (2°) 2f'(v’) The error in the approximate solution v” decreases quadratically with each itera- tion, and thus the rate of convergence for Newton—Raphson method is second-order. Methods that are of higher order than is Newton—Raphson typically have complex iteration procedures that offset their faster rate of convergence. 3.6 Properties of the Method of Division by Leading Coefficients The method of division by leading coefficients is used in Ana to solve systems of linear algebraic equations. The stability and accuracy of this method are limited only by the inexact nature of a binary real number representation. For typical Ana systems of moderate size, these limitations arc not significant. The computational complexity of the method is derived easily. Recall from Chapter 2 that the method reduces an m x m system 05161 +... + Gindm = b; 1<i<m. to an (m — 1) x (m — 1) system by dividing each each equation by its leading coefficient a;,, and then subtracting one equation from the others. This reduction requires m? divisions and m(m — 1) subtractions. The reduction of a n x n system of equations to a single equation thus requires n—-1 > m= n(n + “lien +1) = O(n?) divisions and y m(m — 1) = n(n ~ ‘(en —1)_ fn 1) O(n?) subtractions. Completing the solution by direct substitution requires 3 m= nn + 1) = O(n?) m=1 15 multiplications and nol n(n —1) 2 m=1 subtractions. Thus, the method is O(n) in both multiplications and subtractions. For sparse systems, there are more efficient methods for solving systems of linear equations. For the prototype of Ana, the simplicity of the method of leading coef ficients is desirable; however, the final production version of Ana will use a more efficient sparse method. 16 Chapter 4 Simulating a Changing System 4.1 Introduction During the simulation of a system of gates Gj,...,G, and nodes Nj,...,Nn, the user may at any time alter the data structure, producing a new system with gates Gi,..., Gi and nodes Ni,...,.N/,. When the data structure is changed, the state of the new system must be evolved from the old, maintaining the illusion of a continuous simulation. The techniques Ana uses to evolve system state are the focus of this chapter. The state of a system is fully expressed by the voltages Vi1,...,V;, associated with nodes Nj,...,Nn. To aid the evolution of the system state during changes, this information is redundantly present in the list of gates G1,..., Gig. For a gate Gx with pins numbered 1,...,/,...,p, each pin | is associated with a voltage v;. The voltages v1,..., Vg are used as the state variables for all memory elements contained in the gate G,, because under normal circumstances, VNode(!) = v1. After a data- structure change, however, this may not be true. Re-establishing the condition Vode(t) = U1 VI, VG, while maintaining the illusion of a continuous simulation is the main task of the state-evolution algorithm. LOG reports data-structure changes on an atomic level, as messages describing the alteration of a single gate, node, or parameter. Parameter changes do not affect the structure of the system state; simulation can continue immediately after their receipt. Node and gate operations, however, fundamentally change the system. Most screen-editing operations decompose into multiple node and gate messages, all sent before LOG resumes simulation messages. 4.2 Evolving the System State The algorithm for state evolution consists of two sections. The first section is the response of Ana to each atomic transformation reported by LOG. The second section operates after all atomic changes have made, and re-establishes the condition V Node(1) =U Vi, VG for the new system. The first section is necessary to exchange information from the old system to the new before the latter disappears. The first section of the algorithm is a collection of state-transfer rules for atoms. When a new node is created, its state V; is undefined. When a node N; is split into 17 two new nodes N; and N;, V; and V; retain the value V;. When two nodes N; and N; are combined into a single node N;, V; arbitrarily takes on the value V; or Vz, preferring a defined state. The transfer rules for gates are similar. When a new gate G,, is created, the state of its pins 11,...,v, is undefined. When a copy of a gate is made, the copy keeps the state of the original gate. The second section of the algorithm initializes all undefined nodes and pins. First, all undefined nodes A; are initialized to the defined state v; of an arbitrary pin associated with the node. Then, all undefined pin voltages v; are initialized to the state V; of the node associated with the pin, if defined. Finally, all remaining undefined nodes and pins are set to the reference voltage. The condition Vyyoge(1) = v1 now holds in all situations, except the connection of two defined pins to a single node. In this latter case, the simulation still is permitted to begin. Each gate connected to the node looks to its own v; for state information, and influences the new Viet At for the node, effecting a weighted average of the dissimilar vj’s. After the first timestep of simulation is completed, VNode(t) = UI again holds for the entire system. This algorithm presents an intuitive evolution of state to the user. When a gate is created and added to a circuit, it assumes the state of the appropriate nodes. When a gate is removed from a circuit, it maintains its state. Subsystems can be copied with state intact. After two pins with different states are connected to each other, the simulation displays the resultant “fighting.” At the start of a simulation session, the nodes of a system must “charge up” to a value, which is similar to applying power to a circuit at a lab bench. 4.8 Criterion for Simulating a System In circuit theory, it is easy to create systems that are overconstrained and there- fore have no solution. When using circuit theory to analyze a physical system, over- constrained systems indicate unrealistic component modeling. Future sections de- tail the soft modeling style of Ana, which makes the creation of an overconstrained system virtually impossible. Although the simulation of virtually any system is possible with Ana, there are valid reasons not to simulate certain systems. Generally speaking, there are two types of circuit editing.. Major editing in- volves the schematic capture of a large circuit section, and is primarily a data-entry task. Incremental editing involves the small alteration of an existing system, often in response to simulation results. Simulation during major editing is undesirable. A system under construction does not have a meaningful state, and the heuristic algo- rithm for evolving state may produce senseless results. When system construction is finished, the system state may be random, forcing the user to reset Ana to begin useful simulation. Simulation during incremental editing, however, is essential to the Ana user interface. 18 Ana distinguishes incremental editing from major editing by examining the data structure. Kirchoff’s current law states that the sum of all the current into a node must be zero. Nodes associated with only one pin force the current through the pin to be zero, which is normally an uncharacteristic behavior of a useful circuit. Ana defines a system in which every node is connected to at least two nonmeasurement pins as a complete system, on which major editing is not occurring. Ana simulates only complete systems. This definition works well in practice, except for the oc- casional finished system that is not “complete!” The addition of a small parasitic capacitor to the offending node solves the problem. 19 Chapter 5 The Modeling Style of Ana 5.1 Introduction As specified in Chapter 1, component models in an analog VLSI simulator must be robust, efficient, and functional. To meet these performance requirements, gate models in Ana follow a set of guidelines for robust simulation, and use a library of functions suited for the efficient description of MOS systems. Chapter 6 details the function library; the modeling style is the focus of this chapter. The modeling guidelines address hoth the mathematical form and the behavioral function of a gate description. Mathematically, the preferred method of partial derivative evaluation for the Newton—Raphson method is given, and continuous techniques are shown for describing discontinuous gate bchavior. The functional guidelines dictate parasitic elements in all gates, to prevent overconstrained systems and physically impossible simulation results. 5.2 The Symbolic Evaluation of Partial Derivatives As discussed previously, the behavior of a gate G; with pins 1,...,1,...,p is defined as a set of functions PE, ees PF, weey PE, where @V Node(1) dV Node(p) i dt 7 dt” PE = P¥ (Viece tees VNode(p)» is the current out of Node(!) contributed by pin /. The functions can be redefined with respect to the gate coordinate system, yielding the simpler expression dv dV, PF = PF [Fits ae) By applying the backward Euler method, these functions can be rewritten in finite- difference form. For the solution at a specific time t, + At, the functions become Pi = P (v1,...,Up), where vy; = Vietat To solve a set. of nonlinear algebraic equations that include these functions, the Newton—Raphson method requires the evaluation of the set of partial derivatives OP} OP} Ov,°"""” Oun as well as the function P;’. In the Ana library, the computation of partial derivatives is done by the numer- ical evaluation of the symbolic derivatives of PF, rather than by employing a finite 20 difference method. The symbolic method is more accurate than is that of finite differences, resulting in quicker convergence and simulation stability. When com- puting a function P with its full set of symbolic derivatives, redundant evaluation can be eliminated through clever factoring, lesscning the cfficiency advantage of the finite difference method. 5.3 Modeling Decisions with Fermi Functions The function P* should be continuous with respect to all variables v:, for several reasons. A good initial guess of vy, a 1Up is required for convergence of the Newton— Raphson method; around a discontinuity, such a guess is impossible. In addition, to use the symbolic method of partial-derivative evaluation, the first derivative of PF with respect to all pin potentials must be fully defined. Electrical components, however, often exhibit sharp transitions. A set of switching functions with fully defined derivatives is used in the Ana gate library to describe decisions. The Fermi function has a fully defined first derivative and exhibits the desired strong switching behavior. It is defined as 1 for the domain of all real v. The range of the function is bounded by [0,1]. For v/vy <0, F, > 1, whereas for v/vp > 0, F, > 0. The switching slope at zero is inversely proportional to 4vy. The switching point can be shifted to @ by the substitution v = v' — 6, and the function RF, (v) has the expanded range (0, R]. Fermi functions can be easily used to make more complex decisions. The switch- ing polarity can be reversed with the function F,(v) = 1— F,(v). Given two de- cisions F, (v,) and F, (v2), the binary and decision is F, (v;) F; (ve). With the and and not functions available, any Boolean logic expression can be synthesized. The maximum and minimum functions can also be produced. The expressions max(v1, v2) = uF, (vg — v1) + v2F. (vz — v1) and _ min(v1, vz) = v2 Fe (vz — v1) + 71 Fe (v2 — 01) display the technique. 21 5.4 Behavioral Modeling for a Robnst Simulation Several precautions must be taken in the modeling of components to ensure a stable and sensible simulation. Iuadequale modeling of parasitic capacitances can remove a transient behavior that is necessary to achieve steady state simulation con- ditions. The use of ideal voltage and current sources can result both in unsolvable, overconstrained systems and in underconstrained systems that exhibit physically impossible behaviors. The Ana gate library uses systematic techniques to avoid these problems. To ensure the proper transient behavior of a gate G, with pins 1,...,/,...,p, there must be a capacitive path between each pin J and the other p—1 pins. In addition, there must be a capacitive path between each pin and the reference node. If the physical component does not exhibit parasitic behavior, the capacitance values chosen should be small enough to have negligible effect on simulation accuracy. This interconnection technique cnsures that a gate with only one driven pin has a transient path to steady-state operation. Several parasitic elements are added to voltage and current sources in Ana to prevent simulation difficulties. Linear resistors are added to independent voltage sources to model output impedance. Fermi functions are used to limit independent current sources; for a current source J, connected across a voltage v, the expression i= 1,F, (6-0) limits the output current ¢ when the output voltage is below 6. When parasitic elements cause a qualitative change in independent source behavior, graphical no- tification of limiting appears on the schematic gate symbol. All MOS devices are provided with output impedance; the functional form is shown in Chapter 6. 22 Chapter 6 The MOS Transistor 6.1 Introduction The electrical characteristics of the MOS transistor are well known; Mead and Maher [4] have developed an accurate device model from first principles. The MOS- FET model in Ana is an engineering approximation of a device physics model, which efficiently captures the first-order behavior of the transistor. It is expressed as a combination of simpler functions, which also are useful for manual circuit analysis. These functions are used to describe more complex gates in the Ana library, as shown in later chapters. In Ana, the MOS transistor is modeled as a nonlinear, voltage-controlled current source. The device has three terminals named source, drain, and gate—with volt- age potentials V,,V,, and V, relative to the reference node. Differential voltages are notated with multiple subscripts. The gate is an isolated control terminal, whereas the source aud drain are the current source terminals. The current Jj, is a function of all three potentials. The analysis in this chapter assumes an N-channel device; for a P-channel transistor, reverse the signs of all doubly subscripted variables in the presentation. The behavior of the device is symmetric with respect to Vg,. If Vz, > 0, current flows from drain to source, and [Iz,| = f(Vj.,Va.)- Conversely, for Vz, <0, current flows from source to drain, and |Iz.| = f(Vga,Vas). Note that, if Vz, equals zero, no current flows through the transistor. The behavioral symmetry of the MOS transistor is reflected in the full mathematical symmetry of the Ana model; in the following discussion, features are defined for forward current flow, then extended to the reverse-direction flow. 6.2 A Simplified Nonlinear Current Source As noted, when Vg > 0, current flows from drain to source, and |Jq,| = F(Vgs,Vas). As a first approximation to Ig, for forward current flow, a function I,(Vzo) can be defined. The function has two regions. For 0 < Vus < Vi, where V; is the threshold voltage of the transistor, J, is exponentially dependent on V,,. This subthreshold region has the functional form I, exp(Vgs/Vo), where J, and V, are transistor parameters. For V;, > V;, I, has a square dependence on Vj,. This space-charge limited region continues throughout the normal operating range of the device. 23 By applying current continuity at V,. = Vi, and using Fermi functions, the expression Te (Vos) = Io exp (Vge/Vo) Fe (Vos — Vi) + aV2, Fi (Voge — Vi) can be defined, where a = (I, exp(V;/V,))/V,7. Because of the symmetry of the de- vice, I,(V,a) is an approximation of the reverse current magnitude |Iz,| = f (Vu, Vas) when Vg, < 0. 6.3 Output Impedance Extension The MOS transistor has a finite output impedance. The Ana MOS model approximates this behavior as a linear current dependence on Vz, throughout the model range, as proposed by Early. For forward current flow, the expression I; = I,(Vgs)G(Vas) can be defined, where Vas G(Vas) = (1 + =i) ( ds) Ve and V,, the Early voltage, is a transistor parameter. Likewise, in the reverse dirce tion, where Vz, < 0, the current magnitude can be expressed as I, = I.(Vya)G (Vea). By using Fermi functions, the current magnitude can be approximated over the entire range of Vz, as = I; Fe (Vas) +I, Fe (Vas) : Note that the transition of around Vz, is not smooth. The next section of the chapter addresses this issue. 6.4 Completing the Model The behavior of an MOS transistor around V;, = 0 is dependent on the region of operation. In the subthreshold region, full current is delivered for |Vg,| > Vo. For |Vas| < V,, current magnitude decreases, reaching zero at Vy, = 0. This behavior is approximated by the expression 3V, las = Ig tanh ( i) . ° The hyperbolic tangent argument ensures that Iz, ~ I; when Vg, > Vo. Also note sen(Iz,) = sgn(Vgs), correctly modeling bidirectional device behavior. 24 In the space-charge limited region, current, derating begins at Vz, = Vz, — V; in the forward direction, and at Vsg = Vga — Vi in the reverse direction. Using Fermi functions, the previous equation can be modified to approximate this behavior, producing 3V as las = Ig tanh | ———-_ ] jee a) where _ _ Vi = Voge Fe (Vgs — Vt) Fe (Vas) and V, = Vad Fe (Vga _ V;) F, (Vas) : This expression is the complete steady-state MOS transistor model in the Ana library. In accordance with the modeling guidelines in Chapter 5, the linear capac- itances Cyy, Caz, C'sh, Cys, and Cyq also are included, where 6 is the reference node. Key features of the model are graphed on the next four pages. These graphs are simulation results from Ana. 25 0.8 -- 0.6 + Ids (10-5 A) 0.47- 0.27 0.0 Ids vs. Vgs — Vds=7V, Vt=0.9V 10-3+ 10-85 10-94 Ids (A) 10-12 4 19-18 J 10715 Log Ids vs. Vgs — Vds=7V, Vt=0.9V Vas (V) 26 Ids (10-8 A) Ids (10-8 A) Ids vs. Ves — 0.25V/Step Vds 147 12+ 1.0+ 0.8 + 0.6 + 0.47 27 0.0 Ids vs. Vgs — 10mV/Step Vds 27 Ids vs. Vds — Vgs from 1V 0.25V/Step L27 tot — 08+ ee < 7 = 0.6 + — 3 04+ _—— yy _ ozt 0.0 ' t ft) 1 2 3 4 Vds ({V) . Log Ids vs. Vds — Vgs from 0.1V, 0.1V/Step 10-8 - = yo ~ 10-18 4 3 yo 10-15 | wae 10-18 } } ' ! } Q = Fav] a - a a 2 Vds (10-2 V) 28 Ids (10-8 A) Ide (10-7 A) Vds (10-1 V) so- Ids vs. Vds — Vgs from 0.8V, 0.025V/Step . 25+ 2.0+ 15+ 1.0+ 05+ * i b 4 ‘ 5 Ids vs. V”ds — Vgs from 0.7V, 0.025V/Step Vas (10-1 V) 29 Chapter 7 The Transconductance Amplifier 7.1 Introduction Most analog VLSI circuits can be simulated in Ana by using the MOS transistor model developed in Chapter 6, in conjunction with resistor and capacitor gates. Simulation is more efficient in several ways, however, if atomic models are created for commonly used circuits. In an atomic model, the description of cach transistor can be simplified to reflect its role in the circuit. The model may be accurate for only certain regions of operation, with range checking to indicate improper usage. Nodes that are not accessible to the user can be eliminated, and replaced by a closed-form approximation of subcircuit behavior. The technique of circuit modeling is well illustrated by the transconductance amplifier gate in Ana. The circuit schematic and gate symbol are shown on the next page. The circuit has one active current output, I,.:, which is a function of the four user-accessible potentials Vi, V2, Vse¢, and Voyz, and of the two internal potentials V and V». All six transistors typically operate in the subthreshold range. The output current is a differential amplification of the potentials V; and V2, scaled by a current controlled by Veet. An atomic modeling strategy is easily applied to the transconductance amplifier. The internal nodes corresponding to V and Vy, are eliminated in the Ana gate model. Gate behavior is accurate only for values of V,_ that ensure subthreshold operation of all transistors; the user is informed of incorrect usage by a warning indicator that appears on the symbol. The output impedance of all six circuit transistors are lumped into a single term, and many other simplifications are made. These techniques are described in detail in this chapter. 7.2 Basic Amplification Function The amplification output function Iju:(Vi, Ve, Ieet) can be easily derived, while eliminating the nodes corresponding to the potentials V and V,, from the gate description. As noted on the schematic diagram, I,,; = I, — Jy and I,¢. =, + kh. Dividing Inu: by Jser, and assuming @2 and Qs arc in subthreshold, yiclds the expression Lal -Ih_, exp(Vi-V) —exp(% —V) oul st Ty” exp(Vi — V) + exp(Vg —V)’ where all potentials are scaled by the inverse of V,. A factor of exp(—V) can be eliminated from the fraction, resulting in the expression exp(Vi) — exp(V2) exp(Vi) + exp(V2)" lout = I set 30 The Transconductance Amplifier Cireuit Symbol vag ymbo Ve —4- Qa c Qs Vour ct b- Vi —t Vu hh lour = 1 — Iz y , SET ly id Vour I2 Vi a Qe Qs |- Ve Vv Y ser =, + le Vser [a 31 After algebraic manipulation, the simplified expression Vi — Ve 0 results, where all potentials are rescaled to correct units. As earlier stated, the circuit functions as an amplifier of the difference V,; — V2 over a domain of approxi- mately 4V, volts. The range of the function is scaled by Is-;, which is controlled by Vset. In the following sections, several important additional characteristics of the circuit are modeled, leading to the formulation of the complete function Ipy:. Iout = Iset tanh ( 7.3 Computing the Scaling Current In Section 7.2, the term Ise was not defined. If transistor Q, always is fully on, this definition is simply I set = Le (Veer) ’ where I, is taken from the MOS transistor model definition. However, the Vz, of Q1 may not always be above V,, which is the necessary condition for the transistor to be on. Recall that I,.¢ = I, + Ig. The dominant term in this sum is the current corresponding to the voltage max(Vi, V2). The voltage V is therefore approximately equal to max(Vi, V2) —Veet. If max(Vi, V2) —Veet < Vo, the current: I.(Veee) is linearly derated, as a result of the linear characteristic of the hyperbolic tangent function. The expression Lect = I, (min (Veet, max (Vi, V2))) is a good approximation of this behavior. The min and max functions are imple- mented with Fermi functions, as shown in Chapter 5. 7.4 Computing the Output Impedance The output transistors Qs and Q3 both have a finite output impedance, which should be reflected in the amplifier model. Using the output impedance definition G of the MOS transistor and Fermi functions, the expression Tnmp (Fe(Vi — V2)G (Vout) + Fe(Vi — V2)G@(Vaa — Vout)) supplies the necessary impedance. When a transconductance amplifier is fabricated, the output current function is not always an ideal hyperbolic tangent. One type of error introduced in manu- facturing results in tanh(oo) # —tanh(—oo). Two simulation parameters \, and An, can be added to the previous expression to simulate this effect, resulting in the new expression Tomp (Fe(Vi — V2)G@ (Vout) An + Fe(Vi — V2)G(Vaa — Vout) Av) = Leo 32 Note that A, and A, both default to unity, for an ideal amplifier model. 7.5 Output Voltage Constraints If Vout is too large or too small, the circuit does not function as an amplifier. If Vout is larger than Vgg, the current through transistor Q; changes direction, drawing current from the output. Note that, if Vj > V2, V, of Qs is at a potential Vag — Veer, and significant reverse current flows into Qs for Vout > Vag. However, if Vi < Vo, V, of Qs is at a potential Vgg, and noticeable reverse current flows from Q; only if Vout > Vag + Wsee The addition of the term Ttop =— (F.(Vi _ Ve) Ie (Vout _ Vaa) + F(Vi _ Ve) Ic(Vout + Veet 7 Via)) to Igmp models this effect. If Vout is too small, the differential transistor pair @2 and Q@s3 ccascs to opcrate correctly. If Vo > Vi, V = Vo — Veez during normal operation. If Vou; < Ve — Veer, V is forced to a lower potential to maintain the proper magnitude of current through Qs. Tf Vour< Vi Ver, however, Q, and thus @5 conduct. A large output current results, and the amplifier ceases to function as desired. If Ve < Vi, similar breakdown results. In this case, V = V; — Vs: during normal operation. If Vous < Vi — Veet, V remains at V = Vy — Vy-¢, and the current through transistor Q3 changes direction. If Vou; < Vo — Voce, a significant reverse current flows through Qs; to the output, and the circuit does not operate correctly. For both V2 > Vi and V2 < Vi, the effect of low Vouz can be modeled by the addition of the term Loot = I, (min (Vi, Vo) -~ Vout) 7.6 Completing the Model Using the previous definitions, the circuit is modeled completely by the expres- sion lout = Ltot + Ltop + Loot. The model is accurate only when V,¢ < V;, ensuring subthreshold operation of all transistors for normal V,,:. To meet the transient modeling requirements, parasitic capacitances are added between each pair of nodes, and between each node and ground. Graphs of key model features are shown at the end of the chapter. These graphs are simulation results from Ana. When the circuit is fabricated, the hyperbolic tangent amplifier characteristic is not always centered about V; — V2 = 0. To allow simulation of this error, the simulation parameter 6, is defined. In all the model equations previously presented, 33 VY-VU+ 16,, and V2 — V2 — 165. The default value of 6 is zero, providing an ideal amplifier model. 7.7 The Wide-Range Transconductance Amplifier In many system applications, the restrictive J,,; behavior of the transconduc- tance amplifier cannot be tolerated. In these applications, a variant of the circuit, called the wide-range transconductance amplifier, is used. The circuit schematic and gate symbol are shown on the next page. Except for a less restrictive J: function, the circuit behaves in the same way as the standard transconductance amplifier. Referring to the schematic, the behavior of transistor Qg for low Vou, is symmet- ric Lo the beliavior of transistor Qg for high V,,;. Thus, the wide-range amplifier function Iy.¢ can be deduced from the function Lop to be Lot =— (Fe (V1 _ V2) Lc(—Vout) + E(V _ V2) Lce(—Vout _ Vet) ) . In all other respects, the standard and wide-range transconductance amplifiers are identically modeled in Ana. 34 The Wide Range Transconductance Amplifier Circuit Symbol Vour V1 Vser Va a Qe % IF V1 lour = [1 — Ie yy > Vour Vv Iser — [1 + Ie Vser | Q1 y le ® | iL & 35 Tout (10-10 A) Tout (10-8 A) Iout vs. Vi-V2 - Vset = 0.6V V1-V2 (10-1 V) lout vs. Vi-V2 ~— Vset from 0.6V, 0.025V/Step Vi-ve (10-1 V) 36 Tout (1078 A) Tout (10-9 A) 3.47 3.37 3.27 3.17 3.0 Iout vs. Vout (Standard) — Vset=0.7V Vi=3V V2=2V 3.6 + 3.5 + 3.47 3.37 3.27 3.17 3.0 a _ Nn at aT a Iout vs. Vout (Wide) — Vset=0.7V V1=3V V2=2V 37 Tout (10-9 A) lout (10-9 A) -8.0 7 lout vs. Vout (Standard) — Vset=0.7V V1=2V V2=3V ~3.0 7 ~3.2 7 -9.5+ Vout (V) Iout vs. Vout (Wide) — Vset=0.7V V1=2V V2=3V Vout (V) 38 Chapter 8 Rectification Circuits 8.1 Introduction The circuits described iu Chapter 7 transform a differential voltage into a bidi- rectional current, preserving the sign of the input signal. In applications such as power estimation, demodulation, and absolute-value computation, a unidirectional output signal is desired regardless of the input polarity. ‘he half-wave rectifica- ition operator achieves this result by ignoring input signals of one sign, whereas the full-wave rectification operator produces a single polarity output by processing both positive and negative inputs identically. MOS circuits that implement these func- tions were designed by Massimo Sivilotti at Caltech, and are shown on the next page. The atomic models for both rectification circuits are described in this chapter. Both circuits have one active output Ijyz, which is a function of the voltages Vi, V2, Vset, and Vout. The descriptions of Zoyg contain expressions originally defined for the transconductance amplifier, illustrating the hierarchical nature of the Ana modeling style. 8.2 Basic Rectification Function The basic descriptions of both rectifiers are derived from the transconductance amplifier function Igmp (Vi,V2) = Iset tanh (47%), shown in Chapter 7. For the half-wave rectifier, note that Imi, never can be a negative current. Thus, if Vj > Va, Vmir — Vag to ensure I,,;, = 0. As a result, I,4¢ = 0, and input signals of positive polarity are rejected. When V2 > V,, the current mirror formed by Q, and Q; operates normally, and J,,; is the negation of the amplifier output current. In this manner, only input signals of negative polarity are passed to the output. The expression Tenp (Vis V2) = —Iamp (Vi, V2) Fe(Vi — Vo) captures this behavior. From the schematic, the basic function of the full-wave amplifier is Teng (V1, V2) + Tony (V2,Vi), or, after simplification, Tbrnp (Vis Va) = Tamp (Vi, Va) (Fe(Vi — V2) — (Vi — Va). As desired, this expression is essentially the absolute value of the transconductance amplifier basic function. The output impedance of both circuits is simply the impedance of the active output transistor, which can be expressed by the MOS transistor function G. The two previous equations can be rewritten to include this impedance. It is convenient 39 Circuit Symbol Vi Ve Half Wave Rectifiers Full Wave Mag V1 1] Iour [ ae Vser >— Vour Veo IN I WV lout y Vout Vi lour Vour Vout Ve Vser 40 to include the transconductance amplifier fabrication parameters A», and Ap in this restatement, resulting in the new definitions IP = —A,G(Via — Vout) Iomap (Vi, Vo) and Ih = G(Vaa — Vout) Lamp (Vi, V2) (AnFe(Vi — Vo) — ApFe(Vi — Vo) . 8.3 Output Voltage Constraints The current mirror formed by Qi and Qe prevents the transconductance ampli- fier subfunctions Jpg; and Jyop from affecting rectification behavior, if Vso; is set to ensure subthreshold amplifier operation. Thus, in the half-wave rectifier, the only component influenced by V,y¢ is transistor Q2, the current of which can reverse direction if Voug is sufficiently large. This transistor performs a similar function to the output transistor Q5 in the transconductance amplifier. Following this previous analysis, the expression Ih =~ (F. (Vi _ Vo) Ie (Vout + Veet _ Vaa) + F(V; _ Vo) Ie(Vout _ Via) is obtained. This term is added to J}t; to model the half-wave rectifier completely. From the schematic, the expression In for the full-wave rectifier is simply Tsp (Vi, V2) + Top (V2, Vi). For a functional model, this expression can be approxi- mated as i, = —I,(Vout — Vad + Veet) This term is added to I to model the full-wave rectifier completely. 8.4 Completing the Model The steady-state models for the half-wave and full-wave rectificrs arc complete. These models are accurate for Vsez < Vi, ensuring subthreshold operation of all transistors for normal Vj.;. As in the transconductance amplifier, the simulation parameter 6, is defined to model fabrication variations, and in all previous equations Yy,- V+ $5, and Vy — Vz — bby. Parasitic capacitances are added between each pair of nodes, and between each node and the reference node, to meet transient modeling requirements. Graphs of the simulation results from Ana are shown on the next page. 41 Tout (10-9 A) Tout (1078 A) Tout vs. Vi-V2 (Half—Wave) — Vset: 0.6V to 0.7V 3.5 + 3.0 5 2.6 + p °o 1 rc on ri 1.04 -3 ~2 =1 Q : ‘ ' Vi-v2 (10-1 v) Iout vs. Vi-V2 (Full-Wave) — Vset: 0.6V to 0.7V 0.54 0.0 -4 ~2 -1 Q ‘1 2 Vi-v2 (10-1 V) 42 at Chapter 9 The Horizontal Resistor Circuit 9.1 Introduction The polysilicon resistors available in a standard MOS fabrication process are not suitable for widespread use in analog VLSI systems. High-value resistors consume too much chip area, whereas low-value resistors dissipate an unacceptable amount of power. The horizontal resistor circuit, shown on the next page, provides a nonlinear variable resistance that can replace polysilicon resistors in many applications. Referring to the schematic, the resistor terminals are the nodes associated with potentials Vj, and Voy. The potentials Vj,y and Vaig, are complementary signals that control the resistance value. In the Ana circuit model, the two active currents Tin, aud Ioug ave defined as a fuuction of all four potentials. Vjopy and Viig, are normally set to ensure that all transistors operate in the subthreshold region. 9.2 Basic Resistance Function For the circuit to operate as intended, the control voltages V;,,, and V;,;,,, must be set such that Inign = Tiow = Iset. Given this condition, by conservation of current, fin = Tout = I. Transistors Q3 and Qe carry an equal current 4, and transistors Q@4 and @s5 carry an cqual current Jz, as a result. of circuit symmctry. By Kirchoff’s current law, J = Ig — fh, and Isee = Ig + 4). Dividing I by Iset, and assuming all transistors operate in the subthreshold region, yields the expression ho-h exp(Vin — Vi) — exp(Vout — Vi) l= 1,4.——— = ; et ib+h ° exp (Vin _ V;) + exp (Vout _ Vi) where all potentials are scaled by the inverse of V,. By eliminating a factor of exp(—V;) from the fraction, the previous equation can be rewritten as exp (Vin) _ exp(Vout) exp(Vin) + exp(Voue) : After algebraic manipulation, the simplified expression I= set Vin _— Vout is obtained, where all potentials are rescaled to correct units. Notice that the circuit functions as a linear resistance over a range of approximately 4V, volts. The slope of the linear region, and thus the resistance value, is determined by Ise, which is controlled by the complementary potentials Vj,,, and Vjig,- In the following sections, 43 Circuit Viicu ———4 Q: Thich The Horizontal Resistor Symbol Vincu lin \ Tour Vin ae AV AV AY, > 44 this expression is expanded to model circuit behavior if Thigh F Now, and if V;,, and Vout are both too low or too high for correct operation of Q1 or Qo. 9.8 Definition of Control Currents In this section, complete expressions for the control currents Ij, and Thigh are derived. First consider Jj,,. If transistor Q2 is on and is operating in the subthreshold region, [joy = Ic(Viow). The potentials Vj, and Vout, however, also can affect this current. Note that Ij, is primarily carried by the N-channel transistor (Q4 or Qe) with the highest gate voltage. Thus, the potential V; has the value max(Vin, Vout) — Viow- If this potential is less than V,, the current through transistor Qo is derated. The expression I-(Viow) Fe (Viow _ max(Vin, Vout)) approximates this behavior. The analysis of I,ig, is similar. If transistor Q, is on and is operating in the subthreshold region, [joy = Ic(Vag — Vhigh)- This current also can be affected by the potentials Vj, and Vou. Note that I,ig, is primarily carried by the P-channel transistor (Q3 or Qs) with the lowest gate voltage. Thus, the potential V;, has the value min(Vin, Vout) — (Vaa — Vnign). If this potential exceeds Vag — Vo, the current through transistor @, is derated. The expression T.(Vaa — Vnigh) Fe(min(Vin, Vout) — (Vaa — Viign)) approximates this behavior. As in the transconductance amplifier, when the horizontal resistor circuit is fabricated, the nonlinear resistance function can display the error tanh(co) # — tanh(—oo). The parameters A, and 4, can be added to the previous equations to model this behavior, resulting in the final expressions Low = Ante(Viow) Fe (Viow _ max(Vin, Vout)) and Thigh = ApIc(Vaa — Vaign) Fe (min(Vin, Vout) — (Vag — Viigh)) - If Viow > Ve or Vag — Vaigh > Vt, the circuit is not in the subthreshold region of operation, and the model is not longer accurate. If either condition occurs, a warning indicator appears on the schematic symbol. 45 9.4 Completing the Model The results of Sections 9.2 and 9.3 can be combined with Fermi functions to describe the currents Jj, and Ipy¢. If Ives = tanh (% we") , the definitions Lin = (Fe (Vin _ Vout) ow + F.(Vin _ Vout) Inigh) Tres and Lout = (F (V; — Vout) Inioh + F.(Vin _ out)Iiow) Tres are exact for Inigh = Ttow. If Inigh # Now, the expressions are a suitable approxima- tion for a functional model. To complete the steady-state model, the appropriate output impedance is added to each expression using the MOS transistor function G, producing the final defini- tions Lin, = (FV; _ Vout) G (Vin) Now + F.(Vin _ Vout) G(Vaa _ Vin)Inign) Tres and Jout = (F.(Vin —_ Vout) G(Vaa _— Vous) Thigh + Fr (Viin _ out) O(Vout) Tow) Tres - As in previous circuit models, the simulation parameter 6, is defined to model fabrication variations, and distributed between the potentials V;,, and V,,,. Parasitic capacitances are added between each pair of nodes, and between each node and the reference node, to meet transient model requirements. Simulation results from Ana are shown on the next page. 46 lin (10-9 A) lin vs. Vin-Vout Vlow from 0.6V, 0.025V/Step 1 1 1 T T T -08 -06 -04 -02 00 o2 O04 O8 08 1.0 Vin-Vout (V) 47 Chapter 10 The Ganglion Circuit 10.1 Introduction In biological systems, information often is encoded as the average value of a pulse train of standard height. The ganglion circuit, shown on the next page, imitates this neuronal behavior, generating a pulse stream V,,;¢(¢) that has an average potential proportional to the input current J;,. The pulses switch between Vzg and the reference node, with a time constant set by the control voltage Vj.4,. The Ana model defines the active currents I;, and Ijyz as functions of the potentials V;,, Vouz and Veg. 10.2. Principles of Circuit Operation Referring to the schematic, the transistors Q3, Q4, Qs, and Qg function as a pair of inverters. These transistors can be functionally modeled as a noninverting buffer between V;,, and Vjyz, which sets Vous = Vag if Vin, is greater than the buffer threshold V;,, and sets Vou equal to the reference voltage if Vj, < Ven. It is convenient to analyze qualitative circuit behavior from the initial condition Vin = Vin — AVi. This condition implies V,.; is at the reference voltage, and transistor Qz is off. The capacitor C, charges at a rate detcrmined by Jj, until Vin = Vin. At this instant the buffer switches, forcing the new conditions Vout = Vag and Vj, = Vin + AV2. As a result, transistor Qe is on, and C, discharges at a rate determined by the current Ijegx — Lin, until Vin = Vin. At this point, the buffer again switches, returning Vou: to the reference voltage and setting V;, = Vi, — AV1. The quantities AV; and AV, can be determined easily, using conservation of charge in the system during buffer switching. The instant before the buffer switches to Vout = Vag, capacitors Cy, and C2 are connected in parallel between V;, and the reference node, and the total charge in the system is Q_ = (Ci + C2)Vin. After the buffer switches, Cy and C> form a capacitive divider between Vzg and the reference node, and the total charge in the system is Q4 = C1(Vin +AV2)—Co(Vag—Vin—AV2). Equating Qi and Q_ yields, after algebraic manipulation, the expression Co AV» = (pean 2 VG + Cy ) Vade The same technique can be used to determine AV,. The instant before the buffer output switches from Vz, to the reference voltage, the capacitive voltage divider topology is in place, and the total charge in the system is Q4 = Ci Vi,-C2(Vag—Vin). 48 The Ganglion Circuit Symbol Ce | In lour Vizak Qa Qs In lour Vin >— >— Vour ue Teak C1 49 After the buffer switches, Cy and C2 form the parallel topology, and Q_ — (Cy + C2)(Viz, — AVi). Equating total charge and solving for AV; shows that C2 ) AV, = | >—— ] Vag = AY: as sylumetry would suggest. The pulse duration period, rz, when Vout = Vg, and the pulse refractory period, Tr, When Voyz equals the reference voltage, can both be determined easily. Applying the capacitor definition for C; when Voxz is high gives the expression dV; —AY; 7 = Ci 2 = Lin _ Nreak- Td Leap = Cy Solving for the pulse duration yields ra = ( C1C2 )( Vad C1 + Cy Teak ~~ Lin This technique also can be applied when Voy: is low. The capacitor definition for C71 is _ dVin ,, AVs Leap = Cy dt = re = lin. r Algebraic manipulation yields the final expression rex (goto) (Ma . Cy+Co/ \ Lin} As expected, as Ij, — 0, 7 — oo, and the average value of Vous is the reference voltage. Also, as Ij, — 00, Tg — 0 and 7 — 0, and the average value of Vou: is Vag. 10.3. The Ana Model The Ana ganglion model is not an abstraction of the switching dynamics of the circuit. Rather, the state capacitors Cy and C. remain in the model. Efficient descriptions are substituted for the uoninverling buller Q3...Qg and the leakage circuit Q and Qs. The noninverting buffer can be modeled as a nonlinear, voltage-controlled volt- age source with an output resistance R,. This source can be described using a Fermi function, as Ll Rs Ioug is the sum of J,,, and the current contributed by C4. (VaaFe (Vin — Vin) — Vout) lew = 50 If Vin < Vin, the current Ijeax is set. by Q1 to be T.(Vicaz)- If Vin > Vin, however, the noninverting buffer output is high, Qe is off, and Iieg, = 0. The expression leak = G (Vin) L-(Vieak) Fe (Vin _ Vin) approximates this behavior, including the transistor output impedance. The current Tim is the sum of fieaz and the current contributed by Cy and Co. With the addition of a parasitic capacitor between each pair of nodes, and between each node and the reference node, the ganglion model is complete. The model is correct only if Q1 and Q2 are operating in the subthreshold region; if Vieg, > Vi, a warning indicator appears on the gate symbol. Graphs of Ana simulation results appear on the following pages. 51 Yin (Vv) Vout (VY) 3.07 2.54 2.07 1.57 0.5 + 0.0 Typical Ganglion Switching Waveform — Vin vs. Time 0.0 0.2 0.4 Time 0.6 (10-2 gs) 0.8 1.0 1.2 Typical Ganglion Switching Waveform — Vout vs. Time —— — 0.6 Time (10-2 s) 0.4 0.8 1.0 L2 52 Vout (V¥) Vin (V¥) Ganglion Output Response to Input Current Ramp Time (10-2 s) Ganglion Input Voltage For Input Current Ramp Time (10-2 s) 53 Chapter 11 Topics for Further Research The evolution of Ana from the prototype described in this thesis to a production tool is in many ways a straightforward process. Algorithm refinement and code optimization can improve program efficiency, and the user interface can be enhanced by fully integrating Ana into the LOG environment. An expansion of the gate library, however, presents several difficulties. Creating the complete software definition of an Ana gate is a large task; the horizontal resistor gate, for example, is defined by approximately 1200 lines of Pascal source code, which required 50 hours of programmer time to generate. Recall that for a gate G* with p pins, the Newton-Raphson method requires, for each pin 1, the evaluation of the set of partial derivatives aP# OP Ov,” ” Avy in addition to the behavioral function P}. The generation and efficient coding of these symbolic derivatives are tedious and time-consuming manual tasks. A LOG tool that transforms a set of functional descriptions P . .. PE into an efficient software definition is clearly needed. Standard techniques in compiler de- sign and symbolic mathematical manipulation are applicable to the design of a stimulation assembler. This tool simplifies the conversion of a functional description into a software definition; the generation of the functions Pi ... PP from a circuit schematic remains a manual operation. A stimulation compiler is a tool that generates a closed-form behavioral model of an analog circuit. Using this tool, a hierarchical model of a large analog system can be created easily. Circuit theory provides a compilation algorithm that generates exact descriptions of linear circuits. Unfortunately, there is no known method for generating an exact, closed-form description of an arbitrary nonlinear circuit. Circuits designed in the analog VLSI style developed at Caltech, however, have several interesting semantic properties. Usually, the MOS transistor and the MOS capacitor are the only circuit primitives. Typically, transistors are used either in the subthreshold region or as components in simple logic gates. The MOS capacitor can be considered as a linear element without changing its qualitative behavior in most circuits. In addition, an exact, completely closed-form description of a nonlinear circuit is not necessary in this application. Approximate descriptions, similar to the circuit models presented in this thesis, are sufficient for functional simulation. Eliminating most of the intermediate variables in a circuit model is an acceptable alternative to generating a closed-form expression. 54 Under these weakened source and object constraints, simulation compilation is a tractable research topic. This research may be related to fields as diverse as linear and nonlinear systems theory, deterministic and stochastic estimation the- ory, electronic circuit design, symbolic mathematical manipulation algorithms, and production-rule programming. 55 Bibliography [1]Gupta, Gobal K., Ron Sacks-Davis, and Peter E. Tischer, A Review of Recent Developments in Solving ODEs, ACM Computing Surveys, Vol 17, No 1, pp. 4-47. [2|Scarborough, James B., Numerical Mathematical Analysis, Baltimore, Maryland: John Hopkins University Press, 1958, pp. 192-211, 525-527. [3] Action, Forman S., Numerical Methods That Work, New York, New York: Harper & Row, 1970, pp. 54-55. [4|Mead, Carver A. and Mary Ann C. Maher, “A Charge-Controlled Model for Submicron MOS,” Proceedings of the Colorado Microelectronics Conference, 1986. 56