Bandgap Engineering Silicon Nanopillars Citation Latawiec, Pawel Michal (2013) Bandgap Engineering Silicon Nanopillars. Senior thesis (Major), California Institute of Technology. doi:10.7907/CNP5-BZ88. https://resolver.caltech.edu/CaltechTHESIS:02132018-124953265 Abstract Vertically oriented , bandgap engineered silicon nanopillars were fabricated and addressed. Devices were fabricated via a three dimensional etching process which created sub-5 nm constrictions in silicon radius upon oxidation. This effect was used to create a Coulomb blockade device. Devices were tested at room and liquid nitrogen temperatures. They showed a clear blockade effect distinctive of an asymmetric double tunnel junction at low temperatures which disappeared when tested at higher temperatures. Different device fabrication parameters were also tested to develop high-current devices, including chip anneal time. Furthermore, both device fabrication steps and current flow were modeled and simulated. Item Type: Thesis (Senior thesis (Major)) Subject Keywords: Physics Degree Grantor: California Institute of Technology Division: Physics, Mathematics and Astronomy Major Option: Physics Thesis Availability: Public (worldwide access) Research Advisor(s): Scherer, Axel Group: Kavli Nanoscience Institute Thesis Committee: None, None Defense Date: 7 May 2013 Record Number: CaltechTHESIS:02132018-124953265 Persistent URL: https://resolver.caltech.edu/CaltechTHESIS:02132018-124953265 DOI: 10.7907/CNP5-BZ88 Default Usage Policy: No commercial reproduction, distribution, display or performance rights in this work are provided. ID Code: 10712 Collection: CaltechTHESIS Deposited By: Joy Painter Deposited On: 14 Feb 2018 00:36 Last Modified: 15 Nov 2025 01:30 Thesis Files Preview PDF - Accepted Version See Usage Policy. 10MB Repository Staff Only: item control page

Bandgap Engineering Silicon N anopillars Thesis by Pawel Latawiec In Partial Fulfillment of the Requirements for the Degree of Bachelor of Science California Institute of Technology Pasadena, California 2013 (Submitted May 7, 2013) 11 © 2013 Pawel Lat awiec All Rights Reserved lll Acknowledgements There have been many individuals within Caltech who have m ade my academic journey here a successful and fulfilling one. Dr. Sameer Walavalkar's insight , tutelage, and close mentorship h ave been instrumental in not only helping me work my way around the lab but deciding my future as well. Throughout my four years, both professor Axel Scherer and Tom Tombrello have been invaluable as sources of wisdom and knowledge that only the lucky physicist s are exposed t o at the start of their career. The rest of Prof. Scherer 's group as well as t he always resourceful Kavli Nanoscience Institute st aff deserve special mention for their helpfulness and patience in dealing wit h an undergraduate like myself in t he lab . Their aid is sincerely appreciated. lV Abstract Vert ically oriented , bandgap engineered silicon nanopillars were fabricated and addressed . Devices were fabricated via a t hree dimensional et ching process which created sub-5 nm constrictions in silicon radius upon oxidation. This effect was used to create a Coulomb blockade device. Devices were t est ed at room and liquid nitrogen temperat ures . They showed a clear blockade effect distinctive of an asymmetric double t unnel junction at low t emperatures which disappeared when t est ed at higher t emperatures . Different device fabrication parameters were also test ed t o develop high-current devices, including chip anneal t ime. Furthermore, bot h device fabrication steps and current flow were modeled and simulated. v Contents Acknowledgements iii Abstract IV 1 Introduction 1 1.1 Overview . 1 1.2 Background 2 1.2.1 Charge Transport in N anostructures 2 1.2.2 Non-Equilibrium Green's Function Technique 5 1.2.3 Single Electron Devices . . . . . 7 Etching for Coulomb Blockade Devices 9 1.3 11 2 Methods 2.1 2.2 Fabrication 11 2.1.1 Etching 12 2.1.2 Coulomb Blockade Device 13 2.1.3 Single Electron Transistor 15 Simulation . . . . . . . . . . . . . 17 2.2 .1 17 Thermal Oxidation of Corrugated Silicon N anopillars Vl 2.2 .2 3 Modeling Transport in Silicon Nanopillars 18 Results 25 3.1 Effect of Annealing on Device Performance 25 3.2 Demonstration of Coulomb Blockade 26 3.3 Further Work 30 3.4 Conclusion .. 31 Bibliography 32 1 Chapter 1 Introduction 1.1 Overview Although transistor-like devices h ad been in employ for some time , the modern semiconductor transistor was invented by Moore, Bardeen , Brattain, and Shockley in December 1947, for which the latter three were given a Nobel prize in Physics in 1956. Large and unwieldy, their prototype still bears great similarity to the silicon counterparts we use today. Under the economic imperative of Moore's law , the transistor has seen its size reduced many orders of magnitude by industry. In doing so , semiconductor device m anufacturers of the past half century h ave created a vast and efficient infrast ructure with which to make their chips. Key to silicon 's success as a platform is not its particular semiconducting ch aracteristics , but rather its ability to easily form thin dielectric layers upon oxidation. Meanwhile, the physicists who h ave carried on the tradition of Moore et al. h ave dived to smaller dimensions and more exotic m aterials in their quest for interesting devices. At low temperatures and length scales , quantum effects become important to the operation of fabricated samples , and it is the job of the physicist to tease out 2 their nature and implications. This paper seeks to unite one such novel physical effect, Coulomb blockade, within the existing Complementary Metal-Oxide-Semiconductor (CMOS) platform which entire industries have been built around . By the deterministic nature of the fabrication process, this thesis seeks to model m anufact uring of the device when it can and place important experimental signatures of successful operation within a broader context. The single-electron device presented herein has forged the pat h for reliable and rep eatable single-electron transistors for use in futur e commercial applications. 1.2 Background The primary manufacturing technique this thesis is concerned with is top-down fabricated silicon nanowires. In order to understand the subtleties in nanowire electrical p erform ance, we will review important equations and concepts relevant to charge transport in semiconductor devices. Beginning with a classical formulation of the problem , it will move into a more complete and complex semiclassical description which is relevant as a demonstration of a certain range of experimental sign atures we can discount upon measurement. Finally, the most relevant modeling paradigm for t his paper will be presented and reviewed: the single-electron transistor . 1.2.1 Charge Transport in Nanostructures Within semiconductors, charge transport and conduction is facilitated by two carriers - electrons and holes. An argument due to Landau casts these so-called electrons and 3 holes not as interacting free-sp ace p articles, but rather as quasiparticle charge carriers which carry a (different) effective m ass and no longer interact. The key insight is to picture the particles as lying on the Fermi surface of the m at erial. Briefly, because the charge carriers are confined to the Fermi surface and must stay in place due to the P auli exclusion principle, their scattering cross-section goes to zero. This result implies that we m ay treat these quasiparticles without worrying about the microscopic interactions. With these simplifications in mind , it becomes tractable to form a set of governing equations for transport in semiconductors. (1.1) (1.2) an -=-\7·J +R at n ap -=-\7 · J p +R at (1.3) (1.4) The above relations are known as the Drift-Diffusion Equations. Here, n and p are the densities of electrons and holes carrying charge q with mobilities µn and µP. Likewise, J n and JP are their resp ective electric currents. R is a phenomenological term describing carrier generation and recombination (for inst ance Shockley-ReedHall recombination , an effect which is prominent in cert ain devices) and m ay b e coupled to other variables in the equation. Finally, E describes the electric fi eld. The diffusion coeffi cients are related to the mobility by Dn = µ nk sT / q and DP = µ pksT / q. 4 Equations 1.1 and 1.2 describe the diffusive process of carrier transport as well as the directed , drift process of carrier transport due t o an ext ernal electric field. Equations 1.3 and 1.4 are m ass conservation t erms. In order to self-consistent ly describ e carrier t ransp ort , the Drift-Diffusion Equations are not enough. Because t he carriers themselves possess a charge , they in t urn create external electric fi elds. To account for t his, we must couple in Maxwell 's equations. In order to simplify calculations, we assume we are in t he electrostatic limit. This gives us t he steady-state P oisson 's equation: (1. 5) From equation 1. 5, we can easily derive t he electric fi eld by taking the gradient of t he potential ¢. The unfamiliar terms are Ni and Nfy which represent t he number of acceptor and donor impurit ies in t he semiconductor, resp ectively, and E which gives us t he dielectric constant of the m aterial. Using t hese equations and proper bound ary conditions and device geometry, it is possible to converge on a self-consistent solut ion which solves all of t hem to arbitrary accuracy. This is done by start ing wit h a t herm al background of carriers in the device and altern at ely solving t he Drift -Diffusion and P oisson equations. Figure 2.6 gives an illustration for just such a solut ion in a nanowire device. Note t he I-V plot in figure 2. 5. Alt hough t his equation does provide plenty of flexibility in t he introduction of phenom enological terms, it lacks precision b ecause it ignores important quant um effect s which take place at the nanoscale. 5 1.2.2 Non-Equilibrium Green's Function Technique Although in principle one m ay att empt to solve the Schrodinger 's equation , doing so is intractable. Alternate m ethods to include quantum characteristics in charge transport have been studied. A promising method which was implemented during this thesis was that of Non-Equilibrium Green 's Function (NEGF). Due to its wide use and relatively easy implem entation, it serves as an excellent tool in studying complex nanostructures where quantum effects m ay become important . [10 , 3, 4] Although the Poisson equation rem ains the same , the Drift-Diffusion equations are replaced by their quantum analog. In our case, the device under question is discretized into a real-space grid. The energy at each grid point in the device is determined by the m aterial property and transition rates between grid points are given by the effective mass approximation , with k the wavevector and m* the effective mass, E(k) = ~k2 m* (1.6) Note that the discretization may be done in different ways. For instance, a common practice is to use a tight-binding Hamiltonian and describe atomic orbitals separately. This process results in a matrix which describ es the initial Hamiltonian of the device H 0 . Adding in the charge carrier energy E, the electric potential U, and the self-energy of the device I: , we can define a Green 's function: G = [EI - H 0 - U - I.:] - 1 (1.7) 6 If we define the in-scattering function (1.8) We can get the correlation function (1.9) The self-energy function from the Hamiltonian is given as (1.10) Where the 1, 2, and s subscripts denote scatterings from the first and second leads as well as from the device itself. If we finally define (1.11) then we can use all of these equations to determine important device properties. The density of states is given by the diagonal elements of p. (1.12) And the current at a lead i given by (1.13) 7 Where in both cases we integrate over incoming earner energy E. Again , these equations must be solved self-consistently with the Poisson equation 1.5 , usmg U as the potential term. It is important to note that the current resulting from such calculations is that in ballistic transport - where the carriers do not interact with phonons or scatter from impurities, although it may capture transport and mixing between different subbands of the device. 1.2.3 Single Electron Devices Although the previous methods are quite versatile and can explain a large range of device behavior , they are lacking when discussing strongly non-perturbative effects such as Coulomb blockade. Nonetheless , the theory for single electron device operation is comparatively simple. To illustrate the function of such devices in a somewhat general scenario, we will focus on the single electron transistor (SET). The fund amental unit of the SET is the single electron box (also known as the island or quantum dot) . Due to its small size, the addition of an electron has a large effect on the addition of further electrons. We may write the electron addition energy Ea as (1.14) Where C is the island 's capacitance and Ek is the kinetic energy of the electron in the dot. When this energy is roughly an order of magnitude larger than the thermal energy, we may see charging effects manifest themselves. The inclusion of an electron 8 .... cg v g c1 nl c2 Id/s vd/s n ~--- n2 .... ' Figure 1.1: Schematic demonstrating principles of single electron transistor. A bias voltage is applied across Vd / s and the inner electron box is modulated by V9 . The tunneling barriers are labeled by 1 and 2. Equation 1.15 describes the energy of the full device. raises the energy of the box, thereby prohibiting further electrons from entering. We now refer to figure 1.1. In this fi gure, we note two leads, t he source and drain , as well as a gate modulating the potential of t he electron island. The source and lead are separated by tunnel junctions from the inner island and the gate is capacitively coupled to it . We can write an expression for the total energy of the system[ll]. ( 1.15) The amount of electrons inside the box n is given by n 1 - n 2 , which are the rates of electron flow from the second and first tunnel junction respectively. The capacitances are labeled for their terminal as are the voltages. Furthermore, Cy:, = C9 + C 1 + C 2 . Using this simple equation , we can derive from energy arguments the full range 9 of behavior of single electron devices. We begin at low bias voltages , where t he right half of the equation may be ignored. Here we see that there is no advantage to adding more electrons to t he inner dot so no current flows. However , past a cert ain threshold voltage it does become advantageous for current to fl.ow. If the capacitances of the tunnel junctions are equ al, then t his results in a linear I-V curve past the t hreshold. If t hey are strongly asymmetrical, t hen it is possible for the t unneling rates to be different, result ing in a staircase-like pattern in the IV diagram as the box fills up with electrons. An alternate way to get Coulomb oscillations is to look at t he variations in current due to gate modulation. By changing the Vg term, we can influence central island occupation , resulting in different t unneling rates between the two leads. Once again , a characteristic staircase structure arises from t his consideration . Taken together , these results give "Coulomb diamonds" which are readily seen in transconductance and I-V plots. From t his it is possible to indirectly track electron occupation number within t he dot. 1.3 Etching for Coulomb Blockade Devices Silicon nanowires (SiNWs) have attracted considerable attention as platforms for nanoscale physics experiments over the past twenty years [1 5]. Recent work has used nanowires as cell probes[20], ion sensors[12] , as thermoelectric[26] and as basic electronic components such as SiNWFETs[2]. The fabrication of SiNWs h as progressed along two distinct paths; "Top-Down" 10 and "Bottom-Up." The bottom-up approach concentrates on growing wires using the vapor-liquid-solid technique[2]. Difficulty in specifying nanoparticle size and position has led to most groups relying on stochastic growth techniques. Typically nanowires are grown, cleaved off and suspended in a solvent, spun onto a receptive substrate and then an SEM is required to find appropriate targets for electrical contacting. Although this technique has been used with great success to create innovative devices it is unfortunately limited to the laboratory as it would be difficult to insert into the current CMOS fabrication paradigm. In response, several groups have extended fabrication capabilities to create SiNWs in a top-down method[14 , 21 , 6]. Using a novel three-dimensional etching process of silicon[24] and a self-terminating oxidation, single electron devices were created. The operational principle is to use the increased confinement at pinched regions of the fabricated device to cause an increase in bandgap. This is a well-known result in sub-10 nm diameter silicon nanowires from experiment and tight-binding calculations[23, 25, 16]. Using this increase in bandgap as a tunnel junction, the aim is to create a reproducible, reliable single electron transistor. This effect is schematically shown in figure 2.1 (c). 11 Chapter 2 Methods 2.1 Fabrication Fabrication of devices occurred in the Kavli Nanoscience Institute (KNI) cleanroom . Following standard CMOS techniques, samples were kept in a dust-free cleanroom environment until testing. Aligned electron b eam lithography took place across several steps. The system is a Leica EBPG 5000+. For e-beam lithography for met al lift-off, first a layer of poly-methyl methacrylat e (PMMA) at 23 concentration in anisole (A2) is spun at 4000 RPM on individual chips , then b aked at 180 °C . After electron beam exposure, the chip is developed in 1:3 methyl-isobutyl ketone (MIBK) to isopropanol (IPA) solution for 20 seconds. Initially, alignment pads are defined on the samples with the EBPG and et ched via deep reactive ion et ching a few microns deep. E ach area to be t est ed has three squares of such alignment pads wit h sides of 2 mm , 3 mm , and 4 mm dist ances. These pads serve as markers for subsequent st eps and show up darker during scanning electron microscope (SEM) imaging of the device. The et ched m arker design was chosen due to its robustness to lat er et ching and deposition st eps. The EBPG then uses these to 12 appropriately rotate and then write the subsequent steps. After initial marker construction , the chips are aligned manually before being placed back into the EBPG. Each aligned area contains five separate pillars which are to be addressed individually. The samples are developed and a thin layer of aluminum oxide is sputtered on top. This takes place in a Lesker sputtering system at 20 mTorr in 100: 1 Ar:0 2 atmosphere by sputtering an aluminum target at 400 W. This forms an excellent high-contrast etch mask[6]. After the oxide is deposited, the rest of the PMMA is lifted off by soaking in dichloromethane. 2.1.1 Etching Etching was carried out in an Oxford inductively-coupled plasma reactive ion etcher (ICP-RIE) under a mixed mode etching and passivating process. The silicon was etched under a fluorine chemistry (SF 6 ) and suppressed by formation of a fluorinated polymer from C 4 F 8 . The etching is not reliant on silicon crystal axis. Profile modulation was achieved by varying the ratio of these two gases and the forward power of the etch. This influences the angular distribution of the ions which gives a spread to the etch and creates an undercut. concentrations, the etch undercuts. Under lower passivation. gas To continue the narrowed etch as a vertical sidewall, the forward power is increased and the ions collimated, decreasing their angular distribution. To under-etch the sample , more passivation gas was introduced to the etch chemistry in order to create a stronger buffer layer from the reactive species. By controlling the gas ratios as well as the forward power, a diverse set 13 of structures may be etched. In our case, the etch is continued straight for several hundred nanometers, then pinched in and out twice in rapid succession to create a bead near the base. Such a device is shown in figure 2.l(a). 2.1.2 Coulomb Blockade Device Samples are then oxidized in a furnace at 925 °C until self-terminated. This leaves thin current apertures as effective tunnel barriers in the device. After oxidation, the samples are prepared by spinning a thin layer (200-400 nm) of PMMA on top and baking at 180 °C for five minutes . To remove residual PMMA which possibly wicked up the sides of the pillars , the samples are placed in an oxygen asher for 30 seconds at 75 W power and 300 mTorr. Finally, the samples are developed in buffered hydrofluoric acid (BHF) for 20 seconds, or until the inner silicon core is exposed. This step is often checked by SEM. The PMMA is removed in dichloromethane and the samples are aligned in the EBPG once again under fresh PMMA. After alignment, the top contacts are written to the Coulomb blockade device. Once developed , they are placed in the Lesker sputtering system. Roughly 50-100 nm of titanium are sputtered on the target at 175 W. After this , several hundred nanometers of gold are sputtered at 80 W. This creates a Ti/ Au top contact, wherein the gold serves as a protective layer against titanium oxidation. After the metal is lifted off with dichloromethane, the back side of the sample is swabbed with hydrofluoric acid in order to etch away any remaining thermal oxide. The samples are then placed back in the sputtering system upside-down where aluminum is sputtered on 14 Figure 2.1: Fabrication and schematic of double tunnel junction device. (a) SEM of as-etched, sculpted, silicon nanopillar. Scale bar is lOOnm. (b) TEM of oxidized double tunnel junction pillar after removal from the substrate. Scale bar is 50nm. (c) Schematic placed over the TEM image showing regions of widened silicon bandgap after oxidation. (d) Schematic of the completed device. (e) SEM of the completed device . Scale bar is 500 nm. 15 the back to protect against oxidation and create good contact. Finally, the devices are annealed in a rapid thermal annealer (RTA) under various conditions. Upon completion, the chips are cleaved into smaller subsections and wire bonded onto a chip holder. 2.1.3 Single Electron Transistor Single electron transistor fabrication proceeds similarly. The process flow is shown in figure 2.2. Before the initial decapitation step, a gate contact is defined in the EBPG. A thin layer of titanium (for adhesion) followed by roughly 50 nm of gold is deposited as the gate metal. This is then lifted off in dichloromethane. After this , 200 nm of PMMA are spun on the chip and baked. The sample is placed in type TFA gold etchant for seven seconds. This defines the gate height. The PMMA is dissolved away and a fresh, slightly higher (250-300 nm) layer is spun on. The pillar is then decapitated by a 20 second buffered hydrofluoric acid etch. After removing this PMMA, the pillars are placed in a plasma-enhanced chemical vapor deposition system (PECVD) where a 150 nm layer of silicon dioxide is deposited on the substrate. This protects the top contact and gate from shorting. A layer of PMMA is spun on and the top of the deposited oxide is etched away in a similar fashion as before. This is done separately because of the noticeably different etch rates of thermal and PECVD oxide in BHF. Finally, the samples are prepped for an aligned write on the EBPG. After top contact definition, the process continues as before. 16 Figure 2.2: P rocess flow of transistor manufact ure. Note th at this schematic does not show t he corrugations present in real devices. (1) Etching of silicon . (2) Thermal oxidation unt il self-termination. (3) Deposit ion of gate. (4) Decapitation of t herm al oxide, deposition of PECVD oxide, and second decapitation t hereof. (5) Top contact deposit ion Figure 2.3: Picture showing completed chips after wirebonding to holders. Shown is a 2N222 NP N type t in-can transistor fo r comparison . 17 2.2 Simulation 2.2.1 Thermal Oxidation of Corrugated Silicon Nanopillars Because straightforward etching cannot reach regimes where quantum confinement b ecom es important , further reduction of the active silicon radius is obtained by a selfterminating oxidation process. Since t he original Deal-Grove paper[5] considerable research has been done in describing oxidation rates of surfaces with curvature [S]. Two complementary theories describ e this step . Cui et al cite the creation of a highstress region in the oxidation as inner radius narrows and a subsequent reduction in diffusivity as the reason for a decrease in the reaction rate [l]. Ma et al instead rely on a phenomenological approach and describ e the process via pressure and strain dep endent viscosit ies and reaction rates in the silicon , successfully applying their model to two-dimensional structures [1 3]. A multiphysics model was develop ed which coupled creeping flow of the oxide to oxidant diffusion. Strain dep endence was incorporated via the following: (2.1) (2.2) CJ 8 Vc/(2kT) 'r/ = 'r/o(T) sinh(C!sVc/(2kT)) (2.3) Where CJnn is the normal stress on the oxidation interface , p is the hydrostatic pressure, and Vr , Vd , and Ve are fitting parameters with values from Ma et al [1 3]. D is the 18 diffusivity of oxidant , T/ the viscosity of oxide , and ks the rate of the oxidation reaction. The oxide growth is governed by creeping flow equations in radial coordinates (u is the velocity of the oxide): (2.4) Y'·u=O (2.5) The oxidant diffusion within the silicon dioxide is simply governed by the diffusion equation in radial coordinates: d</> 2 dt = D(p, T)V' </> (2.6) With these simulations, the pinching of bumps from an initially corrugated structure becomes apparent , as in figure 2.4. High-strain regions form on the inner dot surface and regions of great curvature. Furthermore, it is feasible to imagine extending these simulations to entire pillars, although that lies outside the range of possibility with this particular solver. 2.2.2 Modeling Transport in Silicon Nanopillars To get a classical baseline for the current-voltage characteristics of devices, TEMs of small corrugated pillars were digitized and their borders input into a multiphysics modeling program with the classical drift-diffusion and Poisson equations. An image of the simulated structure as well as current plots are given in figures 2.6 and 2.5. Using the framework of NEGF , two separate models were considered. One di- 19 -7 1.5 0.9 0.8 0. 5 0.7 0 0.6 -0.5 0.5 -1 0. 4 -LS 03 0.2 -2 0. 1 -2.5 0 -2 -1 0 1 2 4 5 -3 6 x l0-8 Min : -3.033e-8 Figure 2.4: Oxidation simulation results of a lump in the pillar. Clearly visible are several distinct features: the pinching off of the central bump into a more confined space and the overall fl attening of the outer oxide profile. The overlaid image shows the initial thin oxide shell. The colormap shows the distance of the grown oxide from the starting oxide. The dimensions are given in meters. 20 Vsource(400)=4 Surface: Bectric potential [VJ Max: 4.00 4 -7 3.5 2 3 1.5 2.5 1 2 0.5 1.5 0 1 -0.5 0.5 -0.5 0 0.5 1 1.5 0 xio- 7 Min : -3.103e-3 Figure 2.5: Digitized and simulated pillar taken from TEM of figure 2.l(b) . The colormap shows voltage and the cross section is in cylindrical coordinates. Voltage is applied uniformly on the outer surface just as in a real Coulomb blockade device. mensional toy models were developed and used to study the "first-order" effects of variations and constrictions in the device. A full three-dimensional model in cylindrical coordinates was built which used a coupled-mode space approach in order to simplify computational complexity. Using effective mass and band gap data derived from tight-binding simulations and taking size dimensions from TEMs of oxidized structures, results were compared to theoretical structures which showed large resonant tunneling effects. The mesh was discretized as small as 0.2 nm and solved. Plots shown are IV curves for devices , as in figure 2.7. In order to realistically simulate transport through small constrictions, a coupledmode space approach was used. In this approach , the current flows in the z direction , 21 1 x 10- 5 Current - mock QD system 0.8 ::;:; 0.6 E CJ) 8 0.4 02 0 0 5 x 10- 0.5 1.5 0.5 1.5 7 2 2.5 3 3.5 4 2 2.5 3 3.5 4 Applied Voltage (V) Conductance 4 > :e'6 3 2 Applied Voltage (V) Figure 2.6: Current-voltage and conductance curves for pillar shown in fi gure 2.5 . Although there are some slight nonlinearit ies in the conduct ance , the effects of a double t unnel junction on a classical picture of transport are negligible. 22 - 7 Toy Model - wire vs. 1D hetero structure current 7 ~x~10'--~~~~~~~~~~,--~~~,--~~~.--~~~,-~~~,-~~----, - - hetero structure 6 - - wire 5 4 3 2 0.5 1.5 2 2.5 3 3.5 4 Applied Voltage Figure 2.7: One-dimensional toy models in NEGF showing t he difference in IV plots between effectively one dimensional structures such as het erostructures and structures such as nanopillars. The negative different ial resist ance regions are characteristic of resonant t unneling effects. 23 20 20 15 15 10 10 5 5 0 0 -5 -5 -10 -10 -15 -1 5 5 Figure 2.8: Full three dimensional self-consistent NEGF calculations for toy nanopillars. The left image shows the distribution of silicon and silicon dioxide (blue being silicon), while the right image shows carrier density for an applied voltage. while the x-y direction is discretized. At each point in z direction, the corresponding x-y plane is solved for its eigenmodes and eigenvalues. Then, the Hamiltonian is transformed into this mode-space basis where only the first few low-energy modes are kept. This greatly reduces computation time[22, 18]. This is done by solving for the eigenfunctions in the x-y plane at each point in the z direction. This gives a wavefunction as a function of radial coordinate. The mode Hamiltonian is given as Hmode = utHu (2.7) Where U is constructed from the eigenfunctions and is truncated at mode Nm. This change of basis then ignores modes of energy higher than Nm which in principle may be unimportant for transport. Figure 2.8 shows the carrier density of a simulated device. Due to real imperfec- 24 tions , this model does not encapsulate all of the considerations that go into calculating transport. 25 Chapter 3 Results 3 .1 Effect of Annealing on Device Performance Using the RTA , Coulomb blockade devices of varying initial radius were treat ed with a quick annealing st ep. Annealing is used to obtain good electrical contact between source/drain and device. In this process, titanium is driven into the silicon to form a silicide and establishing conductivity over any native oxide layer that m ay have form ed during processing. A key consideration was t o balance anneal times and rates, as it is well-known that gold under rapidly changing thermal environments refl.ows and m ay resh ape itself. This was mitigated by depositing a thick layer of gold . Figure 3.1 compares behavior of two devices annealed at different t emperatures. Measurements were carried out with a computer controlled volt age supply and pico-ammet er. Each d at a point was polled several times and the mean value and variance of the measured current was kept . Figure 3.2 shows the current-voltage measured for the pillar in 2.l( a) at both room and cryogenic t emperatures. The dat a at cryogenic t emperatures is m arkedly different t han t hat at room t emperature due to reduction of carriers. The results obtained agreed well with Cui et al. [2] Further 26 12 xlO -· Annealed Comparison - - 4soc 10 --20·300 c 8 <: ~ ::> u 4 2 0 -2 0 2 4 6 8 10 12 14 16 Applied Voltage Figure 3.1: Results of different anneal temperatures on performance of nanopillar devices. The anneal at 450 °C shows significant improvement in performance. Note the 300 °C data is scaled by a factor of 30. The noise in this data set is due to sampling only a few points per voltage step. tests used an anneal temperature of 450 °C. 3.2 Demonstration of Coulomb Blockade Devices tested from the smallest initial pillar diameter performed with characteristics of Coulomb blockade. The differential conductance of the cooled sample, shown in figure 3.3 and computed from I-V measurements , displays multiple periodic peaks indicating regular jumps in conductance. At room temperature however , these features disappear and the device shows the exponential current/voltage behavior of a single tunnel junction. The measured behavior of the device at cryogenic temperatures is demonstrative of an asymmetric double tunnel junction[7]. In this case the capacitance, or 'trans- 27 1-V curves for resonant tunneling device at 77K (x15) and 300K 20 18 - 77K (x15) - 300K 16 14 <(' 12 .s 'E 10 !!! ... ::J u 8 6 4 2 00 0.5 1.5 2 2.5 Voltage [VJ 3 3.5 4 Figure 3.2: Measured 1-V plot of a double tunnel junction device at 300K and 77K. Note that the 77K data is scaled by a factor of 15. Clear steps can be seen in the low-temperature measurement. x 5 10 -4 Differential conductance (dl/dV) curves for resonant tunneling device at 77K (x10) and 300K • 77K (x10) • 300K :c 4 "'~ Cl> u c: 3 111 ti ::J "'C c: 0 2 u :'§ 'E 1 ... Cl> Cl> :::: Ci -1 0 0.5 1 1.5 2 2.5 Voltage [VJ 3 3.5 4 F igure 3.3: Differential conductance of a double tunnel junction device at 300K and 77K. P lot was numerically computed from measured 1-V data. Note that the 77K data is scaled by a factor of 10. Periodic peaks can be seen with a spacing of 0.452V. 28 parency,' of one of the junctions is significantly smaller than the other, schematically shown in figure 3.4(a). In our case, for a small forward bias , the first tunnel barrier is easily surpassed and the island is populated with an integer number of charges( figure 3.4( a)). The low transparency of the second barrier keeps the electrons trapped , and the electrostatic repulsion between electrons prevents the island from accumulating more charge. The tunneling coefficient of the opaque barrier, which determines the current allowed through the device, is a function of both the forward bias and the number of charges on the island. The approximate functional dependence can be written as !tunneling rv I 0 (Va , n) x exp(~~r) where o: contains the geometry of the barrier. As the applied voltage is increased , the tunneling rate through the opaque barrier increases but the fixed number of electrons allowed on the island forces the current to remain constant. When the forward bias reaches a large enough value, the electrostatic repulsion can be overcome and an additional electron is forced onto the island(figure 3.4(b)). While the new charge increases the electrostatic repulsion of the island, it is equally negated by the applied voltage; so the voltage increase required to add subsequent electrons remains constant. When the device was measured at room temperature the lack of distinct current steps can be attributed to the addition of thermal noise. The effect of thermal broadening on the distribution of electron energy is to provide a background charge density on the island great enough to effectively remove it from isolation by shorting the more transparent tunnel junction[7]. The resultant structure behaves as a single 29 Low Bias Threshold Room Temperature __n_______r l Figure 3.4: Schematic illust rating t he beh avior of asymmetric double t unnel junction diode under different bias and temperature conditions. (a) At low bias t he island is populated and charged t o saturation . Little charge can t unnel across t he opaque barrier. (b ) At a higher forward bias extra electrons can be for ced into t he island against the electrostatic repulsion of existing charges . The increased number of electrons allows for a great er amount of current to flow t hrough the opaque barrier. (c) At room temperature the t hermal fluctuations remove t he island from isolation effectively creating a single tunnel junction device. 30 rectangular tunnel b arrier (schem atically shown in 3. 4(c)) , displaying the characteristic exponential behavior where I ,...., exp ( °'~t;d ) in which t he o: prefactor contains the relevant geometry of t he barrier. At small voltages (VJwd < 1V ) some small peaks in conductance can b e seen (the red plot in figure 3.3) but t his behavior seems to b e rapidly swamped by t he noise int roduced at higher voltages. Careful measurements made wit h greater precision will be done in t he fut ure t o quant ify t he p ossible presence of Coulomb blockade effects at ro om t emperature. The oscillations present in the differential cond uctance at larger voltages are likely a result of high-energy inj ection effects and not from a blockading effect. 3.3 Further Work It is important to note t hat t he 'semi-classical' treatment of t his device does not include secondary effects such as t he charge dependent modification of t he bandstruct ure or strain effects. We can see hints of t he influence of one of t hese phenomena as the small decrease in current present after each 'st ep ' in t he I-V plot in figure 3.2. (This corresponds to a negative different ial conductance in figure 3.3.) The origin of t he dip in current is believed to come from t he build-up of electrons at t he interface of t he opaque junction. This collection of ch arges opposes t he t unneling of electrons, dropping t he magnit ude of t he current. Careful study of t his b ehavior is required to quant ify t his effect and can be done by either cooling t he sample to liquid helium temperatures or creating a device wit h a greater asymmetry in junction transparency. Fut ure studies will also explore methods to quench t he collection of fr actional ch arge 31 on the island. This ch arge can be measured by examining the I-V curve for asymmetries across zero applied voltage[l 7] . It is hoped t hat the elimination of this excess charge will help to push the Coulomb blockade behavior to higher temperatures. Although many gated structures have been fabricated , the increased difficulty of doing so has made success fleeting. Some devices have shown transistor-like behavior , but due to imperfections none have shown t he classical Coulomb diamond effect. After finally pinning the process down, it is expected that such gated devices will soon be observed. Once a single electron transistor is achieved , more exotic devices may be tested. Previous groups have shown low-temperature single electron logic gates[9] and the potential for spintronic applications [19] . 3.4 Conclusion This thesis summarizes the work done towards the fabrication , modeling , and theoretical understanding of single electron devices created from b andgap engineered silicon nanopillars. Etching dependent geometric modification of the silicon bandstructure was used to create an asymmetric, double tunnel junction energy landscape . Measurements taken at liquid nitrogen temperature show clear Coulomb blockade effects and quantum conductance oscillations. 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