Items where Research Group Name is "Computer Science Technical Reports"

A

Athas, William C. (1983) A VLSI Combinator Reduction Engine. Master's thesis, California Institute of Technology. doi:10.7907/r471-je71. https://resolver.caltech.edu/CaltechTHESIS:03262012-092805759

Ayres, Ronald Frederick (1979) A Language Processor and a Sample Language. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/r2hy-6x63. https://resolver.caltech.edu/CaltechTHESIS:10072021-184918786

B

Barton, Anthony Francis (1980) A Fault Tolerant Integrated Circuit Memory. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/dr7k-qn11. https://resolver.caltech.edu/CaltechTHESIS:03212012-110600634

Browning, Sally Anne (1980) The Tree Machine: A Highly Concurrent Computing Environment. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/15zs-9x82. https://resolver.caltech.edu/CaltechETD:etd-12082006-153626

C

Chen, Wen-Chi (1984) Hierarchy of Graph Isomorphism Testing. Master's thesis, California Institute of Technology. doi:10.7907/pgav-zy26. https://resolver.caltech.edu/CaltechTHESIS:03272012-160759964

Chiang, Chao-Lin (1984) Towards Concurrent Arithmetic: Residue Arithmetic and VLSI. Master's thesis, California Institute of Technology. doi:10.7907/mh9h-1v86. https://resolver.caltech.edu/CaltechTHESIS:04022012-150108167

Choo, Young-il (1983) Hierarchical Nets: A Structured Petri Net Approach to Concurrency. Master's thesis, California Institute of Technology. doi:10.7907/t5w4-vt07. https://resolver.caltech.edu/CaltechTHESIS:04022012-150759898

D

Derby, Howard (1984) Using Logic Programming for Compiling APL. Master's thesis, California Institute of Technology. doi:10.7907/gmjh-z702. https://resolver.caltech.edu/CaltechTHESIS:04092012-134858703

Demetrescu, Stefan Gabriel (1980) A VLSI Based Real-Time Hidden Surface Elimination Display System. Master's thesis, California Institute of Technology. doi:10.7907/Z9GF0RGD. https://resolver.caltech.edu/CaltechTHESIS:04092012-133954577

G

Gray, Moshe (1981) The Design and Implementation of a Reticle Maker for VLSI. Master's thesis, California Institute of Technology. doi:10.7907/0v5p-7011. https://resolver.caltech.edu/CaltechTHESIS:03122018-162127158

H

Holstege, Eric John (1983) Type Inference in a Declarationless, Object-Oriented Language. Master's thesis, California Institute of Technology. doi:10.7907/sa4t-bn94. https://resolver.caltech.edu/CaltechTHESIS:04112012-080413185

Hess, Gideon David (1980) A Software Design System. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/Z9348HB7. https://resolver.caltech.edu/CaltechETD:etd-10182006-082833

J

Johannsen, David Lawrence (1981) Silicon Compilation. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/32ha-8453. https://resolver.caltech.edu/CaltechETD:etd-11092006-140405

K

Kingsley, Christopher Hayden (1982) EARL: An Integrated Circuit Design Language. Master's thesis, California Institute of Technology. doi:10.7907/z452-0r86. https://resolver.caltech.edu/CaltechTHESIS:04112012-082810035

L

Lutz, Christopher (1984) Design of the Mosaic Processor. Master's thesis, California Institute of Technology. doi:10.7907/cs85-zs74. https://resolver.caltech.edu/CaltechTHESIS:04122012-093644670

Lam, Jimmy Kwok-Ching (1983) RTsim: A Register Transfer Simulator. Master's thesis, California Institute of Technology. doi:10.7907/727m-mf30. https://resolver.caltech.edu/CaltechTHESIS:04112012-091046970

Lang, Charles Richard, Jr. (1982) The Extension of Object-Oriented Languages to a Homogeneous, Concurrent Architecture. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/9EVC-2X08. https://resolver.caltech.edu/CaltechETD:etd-09142006-085516

Lin, Tzu-Mu (1981) From Geometry to Logic. Master's thesis, California Institute of Technology. doi:10.7907/887g-zn84. https://resolver.caltech.edu/CaltechTHESIS:04122012-091736952

Lien, Sheue-Ling C. (1981) Toward a Theorem Proving Architecture. Master's thesis, California Institute of Technology. doi:10.7907/ctky-sp95. https://resolver.caltech.edu/CaltechTHESIS:04122012-090812718

Lang, Charles Richard (1980) Automated Wiring Analysis of Integrated Circuit Geometric Data. Master's thesis, California Institute of Technology. doi:10.7907/qxbg-2c10. https://resolver.caltech.edu/CaltechThesis:03092018-151643742

M

Mosteller, Richard Craig (1981) REST: A Leaf Cell Design System. Master's thesis, California Institute of Technology. doi:10.7907/1r9d-ad60. https://resolver.caltech.edu/CaltechTHESIS:04122012-162654185

N

Ngai, John Yee-Keung (1984) The General Interconnect Problem of Integrated Circuits. Master's thesis, California Institute of Technology. doi:10.7907/fgcc-ks03. https://resolver.caltech.edu/CaltechTHESIS:04132012-084100294

Ng, Charles Hok-Bun (1983) FIFO Buffering Transceiver: A Communication Chip Set for Multiprocessor Systems. Master's thesis, California Institute of Technology. doi:10.7907/vdzd-7h35. https://resolver.caltech.edu/CaltechTHESIS:04132012-082850723

O

Oyang, Yen-Jen (1984) HEX: A Hierarchical Circuit Extractor. Master's thesis, California Institute of Technology. doi:10.7907/mptd-b683. https://resolver.caltech.edu/CaltechTHESIS:05022012-105611552

P

Platt, John C. (1985) Sequential Threshold Circuits. Master's thesis, California Institute of Technology. doi:10.7907/fsx9-vh16. https://resolver.caltech.edu/CaltechTHESIS:04122012-104617758

R

Rowson, James Allely (1980) Understanding Hierarchical Design. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/Z9BP00R2. https://resolver.caltech.edu/CaltechETD:etd-12062006-104710

S

Steele, Craig S. (1985) Placement of Communicating Processes on Multiprocessor Networks. Master's thesis, California Institute of Technology. doi:10.7907/kemx-dv57. https://resolver.caltech.edu/CaltechTHESIS:04122012-143033166

Su, Wen-King (1984) Supermesh. Master's thesis, California Institute of Technology. doi:10.7907/yvj1-jt57. https://resolver.caltech.edu/CaltechTHESIS:04122012-161148552

Ségal, Richard Lawrence (1981) Structure, Placement and Modelling. Master's thesis, California Institute of Technology. doi:10.7907/tb24-mg70. https://resolver.caltech.edu/CaltechTHESIS:04132012-091556662

Seiler, Larry Dean (1980) A Pascal Machine Architecture Implemented in Bristle Blocks, a Prototype Silicon Computer. Master's thesis, California Institute of Technology. doi:10.7907/Z9VH5KTT. https://resolver.caltech.edu/CaltechTHESIS:03122018-143833053

T

Trawick, David James (1983) Robust Sentence Analysis and Habitability. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/re17-h091. https://resolver.caltech.edu/CaltechETD:etd-11032005-154728

W

Whiting, Douglas Lee (1985) Bit-Serial Reed-Solomon Decoders in VLSI. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/bjd1-9j44. https://resolver.caltech.edu/CaltechETD:etd-03252008-090414

Whiting, Douglas Lee (1982) A Self-Timed Chip Set for Microprocessor Communication. Master's thesis, California Institute of Technology. doi:10.7907/tnv1-t713. https://resolver.caltech.edu/CaltechTHESIS:04122012-110450092

Whitney, Telle (1981) A Hierarchical Design Rule Checker. Master's thesis, California Institute of Technology. doi:10.7907/dqz1-c122. https://resolver.caltech.edu/CaltechTHESIS:04122012-100224959

Whelan, Daniel Steven (1981) A Versatile Ethernet Interface. Master's thesis, California Institute of Technology. doi:10.7907/x4t9-5n88. https://resolver.caltech.edu/CaltechTHESIS:04122012-112531771